Texas-instruments TMS320TCI6486 Manual de usuario Pagina 1

TMS320C6472/TMS320TCI6486 DSPEthernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) ModuleUser's GuideLiterature Number: SPR

PrefaceSPRUEF8F–March 2006–Revised November 2010Read This FirstAbout This ManualThis document provides a functional description of the Ethernet Media

EMAC Port Registerswww.ti.com5.6 Receive Teardown Register (RXTEARDOWN)The receive teardown register (RXTEARDOWN) is shown in Figure 48 and described

www.ti.comEMAC Port Registers5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)The transmit interrupt status (unmasked) register (TXINTS

EMAC Port Registerswww.ti.com5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)The transmit interrupt status (masked) register (TXINTST

www.ti.comEMAC Port Registers5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)The transmit interrupt mask set register (TXINTMASKSET) is shown i

EMAC Port Registerswww.ti.com5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)The transmit interrupt mask clear register (TXINTMASKCLEAR) i

www.ti.comEMAC Port Registers5.11 MAC Input Vector Register (MACINVECTOR)The MAC input vector register (MACINVECTOR) is shown in Figure 53 and describ

EMAC Port Registerswww.ti.com5.12 MAC End-of-Interrupt Vector Register (MACEOIVECTOR)The MAC end-of-interrupt vector register (MACEOIVECTOR) is shown

www.ti.comEMAC Port Registers5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)The receive interrupt status (unmasked) register (RXINTST

EMAC Port Registerswww.ti.com5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)The receive interrupt status (masked) register (RXINTSTA

www.ti.comEMAC Port Registers5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)The receive interrupt mask set register (RXINTMASKSET) is shown in

User's GuideSPRUEF8F–March 2006–Revised November 2010C6472/TCI6486 EMAC/MDIO1 IntroductionThis document provides a functional description of the

EMAC Port Registerswww.ti.com5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)The receive interrupt mask clear register (RXINTMASKCLEAR) is

www.ti.comEMAC Port Registers5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)The MAC interrupt status (unmasked) register (MACINTSTATRAW)

EMAC Port Registerswww.ti.com5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)The MAC interrupt status (masked) register (MACINTSTATMASKE

www.ti.comEMAC Port Registers5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)The MAC interrupt mask set register (MACINTMASKSET) is shown in Figur

EMAC Port Registerswww.ti.com5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown

www.ti.comEMAC Port Registers5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register(RXMBPENABLE)The receive multicast/broadcast/promiscu

EMAC Port Registerswww.ti.comTable 57. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) FieldDescriptions (continued)Bit

www.ti.comEMAC Port RegistersTable 57. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) FieldDescriptions (continued)Bit

EMAC Port Registerswww.ti.com5.22 Receive Unicast Enable Set Register (RXUNICASTSET)The receive unicast enable set register (RXUNICASTSET) is shown in

www.ti.comEMAC Port Registers5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)The receive unicast clear register (RXUNICASTCLEAR) is shown in Figur

EMIC0CPPIbuffermanager+CPPIRAM0EMAC0DMAmemorytransfercontrolPeripheralbusMDIOEMAC1CPPIbuffermanager+CPPIRAM1EMIC1ToGEMsToGEMsMII0/GMII0RGMII0

EMAC Port Registerswww.ti.com5.24 Receive Maximum Length Register (RXMAXLEN)The receive maximum length register (RXMAXLEN) is shown in Figure 66 and d

www.ti.comEMAC Port Registers5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)The receive buffer offset register (RXBUFFEROFFSET) is shown in Figur

EMAC Port Registerswww.ti.com5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)The receive filter low priority frame thresh

www.ti.comEMAC Port Registers5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)The receive channel 0-7 flow control threshold re

EMAC Port Registerswww.ti.com5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)The receive channel 0-7 free buffer count register (RX

www.ti.comEMAC Port Registers5.29 MAC Control Register (MACCONTROL)The MAC control register (MACCONTROL) is shown in Figure 71 and described in Table

EMAC Port Registerswww.ti.comTable 65. MAC Control Register (MACCONTROL) Field Descriptions (continued)Bit Field Value Description12 RXFIFOFLOWEN Rece

www.ti.comEMAC Port Registers5.30 MAC Status Register (MACSTATUS)The MAC status register (MACSTATUS) is shown in Figure 72 and described in Table 66.F

EMAC Port Registerswww.ti.comTable 66. MAC Status Register (MACSTATUS) Field Descriptions (continued)Bit Field Value Description15-12 RXERRCODE Receiv

www.ti.comEMAC Port Registers5.31 Emulation Control Register (EMCONTROL)The emulation control register (EMCONTROL) is shown in Figure 73 and described

www.ti.comIntroductionThe EMAC module provides an efficient interface between the TCI6486/C6472 core processor and thenetworked community. The EMAC su

EMAC Port Registerswww.ti.com5.32 FIFO Control Register (FIFOCONTROL)The FIFO control register (FIFOCONTROL) is shown in Figure 74 and described in Ta

www.ti.comEMAC Port Registers5.33 MAC Configuration Register (MACCONFIG)The MAC configuration register (MACCONFIG) is shown in Figure 75 and described

EMAC Port Registerswww.ti.com5.34 Soft Reset Register (SOFTRESET)The soft reset register (SOFTRESET) is shown in Figure 76 and described in Table 70.F

www.ti.comEMAC Port Registers5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)The MAC source address low bytes register (MACSRCADDRLO) is show

EMAC Port Registerswww.ti.com5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)The MAC source address high bytes register (MACSRCADDRHI) is sh

www.ti.comEMAC Port Registers5.37 MAC Hash Address Register 1 (MACHASH1)The MAC hash registers allow group addressed frames to be accepted on the basi

EMAC Port Registerswww.ti.com5.38 MAC Hash Address Register 2 (MACHASH2)The MAC hash address register 2 (MACHASH2) is shown in Figure 80 and described

www.ti.comEMAC Port Registers5.39 Back Off Test Register (BOFFTEST)The back off test register (BOFFTEST) is shown in Figure 81 and described in Table

EMAC Port Registerswww.ti.com5.40 Transmit Pacing Algorithm Test Register (TPACETEST)The transmit pacing algorithm test register (TPACETEST) is shown

www.ti.comEMAC Port Registers5.41 Receive Pause Timer Register (RXPAUSE)The receive pause timer register (RXPAUSE) is shown in Figure 83 and described

Introductionwww.ti.comTable 2. EMAC1_EN Pin Description (continued)Value Description1 EMAC1 is enabled and used.Pulls on EMAC1 I/O are disabled (excep

EMAC Port Registerswww.ti.com5.42 Transmit Pause Timer Register (TXPAUSE)The transmit pause timer register (TXPAUSE) is shown in Figure 84 and describ

www.ti.comEMAC Port Registers5.43 MAC Address Low Bytes Register (MACADDRLO)The MAC address low bytes register (MACADDRLO) is shown in Figure 85 and d

EMAC Port Registerswww.ti.com5.44 MAC Address High Bytes Register (MACADDRHI)The MAC address high bytes register (MACADDRHI) is shown in Figure 86 and

www.ti.comEMAC Port Registers5.45 MAC Index Register (MACINDEX)The MAC index register (MACINDEX) is shown in Figure 87 and described in Table 81.Figur

EMAC Port Registerswww.ti.com5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)The transmit channel 0-7 DMA head descriptor point

www.ti.comEMAC Port Registers5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)The receive channel 0-7 DMA head descriptor pointer

EMAC Port Registerswww.ti.com5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)The transmit channel 0-7 completion pointer register (TXnCP)

www.ti.comEMAC Port Registers5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)The receive channel 0-7 completion pointer register (RXnCP) i

EMAC Port Registerswww.ti.com5.50 Network Statistics RegistersThe EMAC has a set of statistics that record events associated with frame traffic. The s

www.ti.comEMAC Port Registers5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES)The total number of good multicast frames received on the EMAC. A

www.ti.comEMAC Functional Architecture2 EMAC Functional ArchitectureThis section discusses the architecture and basic function of the EMAC peripheral.

EMAC Port Registerswww.ti.com5.50.7 Receive Oversized Frames Register (RXOVERSIZED)The total number of oversized frames received on the EMAC. An overs

www.ti.comEMAC Port Registers5.50.11 Filtered Receive Frames Register (RXFILTERED)The total number of frames received on the EMAC that the EMAC addres

EMAC Port Registerswww.ti.com5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)The total number of good broadcast frames transmitted on the EM

www.ti.comEMAC Port Registers• Was any size• Had no carrier loss and no underrun• Experienced one collision before successful transmission. The collis

EMAC Port Registerswww.ti.com5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)The total number of frames on the EMAC that experienced ca

www.ti.comEMAC Port Registers5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)The total number of 256-byte to 511-byte fram

EMAC Port Registerswww.ti.com5.50.34 Receive FIFO or DMA Start-of-Frame Overruns Register (RXSOFOVERRUNS)The total number of frames received on the EM

www.ti.comAppendix A GlossaryBroadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet deviceson the local network. The

Appendix Awww.ti.comJumbo Packets— Jumbo frames are defined as those packets whose length exceeds the standardEthernet MTU, which is 1500 kbytes. For

www.ti.comAppendix B Revision HistoryThis revision history highlights the technical changes made to the document in this revision.Table 87. EMAC/MDIO

EMAC Functional Architecturewww.ti.com2.1.3 GMII ClockingThe GMII interface is available only on EMAC0 and requires two clock sources generated intern

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

www.ti.comEMAC Functional Architecture2.3 System-Level ConnectionsOn the TCI6486/C6472 device, EMAC0 and EMAC1 support the following different types o

MTCLKMTXD[3−0]MTXENMCOLMCRSMRCLKMRXD[3−0]MRXDVMRXERMDCLKMDIO2.5 MHZor25 MHzPhysicallayerdevice(PHY)SystemcoreEMACMDIOTransformerRJ-45EMAC Functional A

www.ti.comEMAC Functional ArchitectureTable 7. EMAC and MDIO Signals for MII InterfaceSignal Name I/O DescriptionMTCLK I Transmit clock (MTCLK). The t

2SPRUEF8F–March 2006–Revised November 2010Submit Documentation FeedbackCopyright © 2006–2010, Texas Instruments Incorporated

MDCLKMDIORMTXD[1−0]RMTXENRMCRSDVRMRXD[1−0]RMRXERPhysicallayerdevice(PHY)EMACMDIOSystemcoreRMREFCLK RMREFCLK50-MHzzero-delayclock buffer50-MHzXOEMAC Fu

MTCLKMTXD[7−0]MTXENMCOLMCRSMRCLKMRXD[7−0]MRXDVMRXERMDCLKMDIOPhysicallayerdevice(PHY)SystemcoreTransformer2.5 MHz,25 MHz,or 125 MHzRJ−45EMACMDIOGMTCLKw

EMAC Functional Architecturewww.ti.comTable 9. EMAC and MDIO Signals for GMII InterfaceSignal Name I/O DescriptionMTCLK I Transmit clock (MTCLK). The

RGTXCRGTXD[3−0]RGTXCTLRGREFCLKRGRXCRGRXD[3−0]RGRXCTLRGMDCLKRGMDIOPhysicallayerdevice(PHY)SystemcoreTransformer2.5 MHz25 MHz,or 125 MHzRJ−45EMACMDIOwww

EMAC Functional Architecturewww.ti.comTable 10. EMAC and MDIO Signals for RGMII Interface (continued)Signal Name I/O DescriptionRGRXCTL I Receive cont

TX_CLKTXDTX_SYNCRX_CLKRXDRX_SYNCMDCLKMDIOEMACMDIOSystemcorePhysicallayerdevice(PHY)MHZ_125_CLK125-MHzzero-delayclockbuffer125-MHzXOwww.ti.comEMAC Fun

EMAC Functional Architecturewww.ti.comTable 11 summarizes the individual EMAC and MDIO signals for the S3MII interface.Table 11. EMAC and MDIO Signals

TXDTX_SYNCTX_CLKRXDRX_SYNCRX_CLKMHZ_125_CLKDevice #1TXDTX_SYNCTX_CLKRXDRX_SYNCRX_CLKMHZ_125_CLKDevice #2TXDTX_SYNCTX_CLKRXDRX_SYNCRX_CLKMHZ_125_CLKDev

TXDTX_SYNCTX_CLKRXDRX_SYNCRX_CLKMHZ_125_CLKDevice #1TXDTX_SYNCTX_CLKRXDRX_SYNCRX_CLKMHZ_125_CLKDevice #2TXDTX_SYNCTX_CLKRXDRX_SYNCRX_CLKMHZ_125_CLKDev

PreambleSFDDestinationSourceLen Data7 1 6 6 2 46 − (RXMAXLEN - 18) 4FCSNumber of bytesLegend: SFD = Start Frame Delimiter; FCS = Frame Check Sequence

Preface ... 101 Int

EMAC Functional Architecturewww.ti.com2.4.2 Multiple Access ProtocolNodes in an ethernet local area network are interconnected by a broadcast channel.

www.ti.comEMAC Functional Architecture2.5 Programming Interface2.5.1 Packet Buffer DescriptorsThe buffer descriptor is a central part of the EMAC modu

SOP | EOP600 60pBufferpNextPacket A60 bytes0SOPPacket BFragment 1512 bytes5121514pBufferpNextEOP00−−−Packet BFragment 3500 bytes502pBuffer−−−500pNext−

www.ti.comEMAC Functional ArchitectureTo add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, thesoftware

EMAC Functional Architecturewww.ti.com2.5.4 Transmit Buffer Descriptor FormatA transmit (TX) buffer descriptor (Figure 12) is a contiguous block of fo

www.ti.comEMAC Functional Architecture2.5.4.1 Next Descriptor PointerThe next descriptor pointer indicates the 32-bit word aligned memory address of t

EMAC Functional Architecturewww.ti.com2.5.4.7 End-of-Packet (EOP) FlagWhen set, this flag indicates that the descriptor points to the last packet buff

www.ti.comEMAC Functional Architecture2.5.5 Receive Buffer Descriptor FormatA receive (RX) buffer descriptor (Figure 13) is a contiguous block of four

EMAC Functional Architecturewww.ti.com2.5.5.1 Next Descriptor PointerThe next descriptor pointer indicates the 32-bit word aligned memory address of t

www.ti.comEMAC Functional Architecture2.5.5.7 End-of-Packet (EOP) FlagWhen set, this flag indicates that the descriptor points to the last packet buff

www.ti.com4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ... 864.12 MDIO User Access Register 0 (USERA

EMAC Functional Architecturewww.ti.com2.5.5.16 Control FlagThe EMAC sets this flag in the SOP buffer descriptor if the received packet is an EMAC cont

TXpacerandinterruptcombinerRXpacerandinterruptcombinerMACTXINT0MACRXINT0Commoninterruptcombiner MACINT0TXpacerandinterruptcombiner MACTX

PacingblockTimed-delaySMDIV_NEXTDivideSMEVT_TIMEDEVT_DIVEVT_OUTPS_TICKEVT_INEMAC Functional Architecturewww.ti.com2.7.1 Pacing BlockIn simple terms

WaitingDelayTime=0Time=0OutputEVT_PULSE=0 &&DIV_NEXT=1EVT_PULSE=1&&TIME< TIME_CFGEVT_PULSE=1&&DIV_NEXT=1PS_TICK=1&&

WaitingCountOutputEVT_PULSE=0(or)EVT_PULSE=1&&CNT >=CNT_CFG&& TIME_CFGI=0IncrementCNTCNT=1EVT_PULSE=0&&CR=0EVT_PULSE

PacingblockTXEVT[0]PacingblockTXEVT[1]EW_INTCTL[8]EW_INTCTL[9]PacingblockTXEVT[2]PacingblockTXEVT[3]EW_INTCTL[10]EW_INTCTL[11]PacingblockTXEVT[4]

PacingblockRXEVT[0]PacingblockRXEVT[1]EW_INTCTL[16]EW_INTCTL[17]PacingblockRXEVT[2]PacingblockRXEVT[3]EW_INTCTL[18]EW_INTCTL[19]PacingblockRXEVT[

EW_INTCTL[1]EW_INTCTL[2]EW_INTCTL[3]EW_INTCTL[4]EW_INTCTL[4:1]MACINTCommoninterruptcombinerblockHOSTSTATMDIO_LINTMDIO_USERwww.ti.comEMAC Functional

EMICmoduleControlregistersandlogicPHYmonitoringPeripheralclockMDIOclockgeneratorUSERINTMDIOinterfacePHYpollingMDCLKMDIOLINKINTConfigurationbusEMAC F

www.ti.comEMAC Functional Architecture2.8.2 MDIO Module Operational OverviewThe MDIO module implements the 802.3 serial management interface to simult

www.ti.com5.43 MAC Address Low Bytes Register (MACADDRLO) ... 1415.44 MAC Address High Bytes

EMAC Functional Architecturewww.ti.com2.8.2.2 Writing Data to a PHY RegisterThe MDIO module includes a user access register (USERACCESSn) to directly

www.ti.comEMAC Functional ArchitectureThe implementation of these macros using the register layer Chip Support Library (CSL) is shown inExample 3 (USE

ClockandresetlogicReceiveDMA engineInterruptcontrollerTransmitDMA engineControlregistersEMICReceiveFIFOMACreceiverStateRAMStatisticsTransmitFIFOMACt

www.ti.comEMAC Functional Architecturecan be sent to only a single channel.• The transmit path:– Transmit DMA engineThe transmit DMA engine performs t

EMAC Functional Architecturewww.ti.comAn interrupt is issued to the CPU whenever a transmit or receive operation has completed. However, it isnot nece

www.ti.comEMAC Functional ArchitectureReceive buffer flow control is triggered when the number of free buffers in any enabled receive channel(RXnFREEB

EMAC Functional Architecturewww.ti.com• Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames).• The 32-bit frame-check sequen

www.ti.comEMAC Functional Architecture2.10.2.5 Back OffThe EMAC implements the 802.3 binary exponential back-off algorithm.2.10.2.6 Transmit Flow Cont

EMAC Functional Architecturewww.ti.com2.10.2.7 Speed, Duplex, and Pause Frame SupportThe MAC can operate in half-duplex or full-duplex mode at 10 Mbps

www.ti.comEMAC Functional ArchitectureA MAC address location in RAM is 53 bits wide and consists of:• 48 bits of the MAC address• 3 bits for the chann

www.ti.comList of Figures1 EMAC and MDIO Block Diagram... 122 Eth

EMAC Functional Architecturewww.ti.com2.11.6 Receive Channel TeardownThe host commands a receive channel teardown by writing the channel number to the

www.ti.comEMAC Functional Architecture2.11.8 Promiscuous Receive ModeWhen the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RX

EMAC Functional Architecturewww.ti.comTable 14. Receive Frame Treatment Summary (continued)Address RXMBPENABLE BitsMatchRXCAFEN RXCEFEN RXCMFEN RXCSFE

www.ti.comEMAC Functional Architecture• Initialize the TXnHDP registers to zero.• Enable the desired transmit interrupts using the TXINTMASKSET and TX

EMAC Functional Architecturewww.ti.comFor example, for 1000-Mbps operation, these restrictions translate into the following rules:• For the short-term

www.ti.comEMAC Functional Architecture2.16 Initialization2.16.1 Enabling the EMAC/MDIO PeripheralWhen the device is powered on, the EMAC peripheral is

EMAC Functional Architecturewww.ti.comIf the MDIO module must operate on an interrupt basis, the interrupts can be enabled at this time usingthe USERI

www.ti.comEMAC Functional ArchitectureConfiguration register (EMACCFG), found at device level.20. Enable the device interrupt in EW_INTCTL.2.17 Interr

EMAC Functional Architecturewww.ti.comUpon interrupt reception, the CPU processes one or more packets from the buffer chain and thenacknowledges one o

www.ti.comEMAC Functional Architecture2.17.2.1 Link Change InterruptThe MDIO module asserts a link change interrupt (LINKINT) if there is a change in

www.ti.com48 Receive Teardown Register (RXTEARDOWN) ... 10049 Transmit Interrupt St

EMAC Functional Architecturewww.ti.comWhen the emulation suspend state is entered, the EMAC will stop processing receive and transmit framesat the nex

www.ti.comEMIC Module Registers3 EMIC Module Registers3.1 EW_INTCTL RegistersThere are six EW_INTCTL registers (one per C64x+ megamodule). These regis

EMIC Module Registerswww.ti.comFigure 24. RPCFG Register31 28 27 16Reserved TIME_CFG0000 R/W-0000 000015 8 7 4 3 2 1 0CNT_CFG Reserved TU CU TR CRR/W-

www.ti.comEMIC Module Registers3.2.2 RPSTAT RegistersThere are eight RPSTAT registers (RPSTAT0 thru RPSTAT7), one per receive event. This registerconf

EMIC Module Registerswww.ti.com3.3 TPIC Registers3.3.1 TPCFG RegistersThere are eight TPCFG registers (TPCFG0 through TPCFG7), one per transmit event.

www.ti.comEMIC Module Registers3.3.2 TPSTAT RegistersThere are eight TPSTAT registers (TPSTAT0 through TPSTAT7), one per transmit event. This register

MDIO Registerswww.ti.com4 MDIO Registers4.1 IntroductionTable 21 lists the memory-mapped registers for the Management Data Input/Output (MDIO). For th

www.ti.comMDIO Registers4.2 MDIO Version Register (VERSION)The MDIO version register (VERSION) is shown in Figure 29 and described in Table 22.Figure

MDIO Registerswww.ti.com4.3 MDIO Control Register (CONTROL)The MDIO control register (CONTROL) is shown in Figure 30 and described in Table 23.Figure

www.ti.comMDIO Registers4.4 PHY Acknowledge Status Register (ALIVE)The PHY acknowledge status register (ALIVE) is shown in Figure 31 and described in

www.ti.comList of Tables1 Serial Management Interface Pins ... 132

MDIO Registerswww.ti.com4.5 PHY Link Status Register (LINK)The PHY link status register (LINK) is shown in Figure 32 and described in Table 25.Figure

www.ti.comMDIO Registers4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)The MDIO link status change interrupt (unmasked) registe

MDIO Registerswww.ti.com4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)The MDIO link status change interrupt (masked) register

www.ti.comMDIO Registers4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)The MDIO user command complete interrupt (unmasked) r

MDIO Registerswww.ti.com4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)The MDIO user command complete interrupt (masked) re

www.ti.comMDIO Registers4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)The MDIO user command complete interrupt mask set

MDIO Registerswww.ti.com4.11 MDIO User Command Complete Interrupt Mask Clear Register(USERINTMASKCLEAR)The MDIO user command complete interrupt mask c

www.ti.comMDIO Registers4.12 MDIO User Access Register 0 (USERACCESS0)The MDIO user access register 0 (USERACCESS0) is shown in Figure 39 and describe

MDIO Registerswww.ti.com4.13 MDIO User PHY Select Register 0 (USERPHYSEL0)The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 40 and

www.ti.comMDIO Registers4.14 MDIO User Access Register 1 (USERACCESS1)The MDIO user access register 1 (USERACCESS1) is shown in Figure 41 and describe

www.ti.com47 MAC Input Vector Register (MACINVECTOR) Field Descriptions ... 10548 MAC End-of-Interrupt Ve

MDIO Registerswww.ti.com4.15 MDIO User PHY Select Register 1 (USERPHYSEL1)The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 42 and

www.ti.comEMAC Port Registers5 EMAC Port RegistersTable 36 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). For them

EMAC Port Registerswww.ti.comTable 36. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description See15Ch RX7FRE

www.ti.comEMAC Port RegistersTable 36. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description See65Ch TX7CP

EMAC Port Registerswww.ti.comTable 36. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description See27Ch FRAME1

www.ti.comEMAC Port Registers5.1 Transmit Identification and Version Register (TXIDVER)The transmit identification and version register (TXIDVER) is s

EMAC Port Registerswww.ti.com5.2 Transmit Control Register (TXCONTROL)The transmit control register (TXCONTROL) is shown in Figure 44 and described in

www.ti.comEMAC Port Registers5.3 Transmit Teardown Register (TXTEARDOWN)The transmit teardown register (TXTEARDOWN) is shown in Figure 45 and describe

EMAC Port Registerswww.ti.com5.4 Receive Identification and Version Register (RXIDVER)The receive identification and version register (RXIDVER) is sho

www.ti.comEMAC Port Registers5.5 Receive Control Register (RXCONTROL)The receive control register (RXCONTROL) is shown in Figure 47 and described in T