Texas Instruments TMS320C6722 Manual de usuario descargar pdf (Pagina 38)

www.ti.com

4.8 Reset

4.8.1 Reset Electrical Data/Timing

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

SPRS268E – MAY 2005 – REVISED JANUARY 2007

A hardware reset ( RESET) is required to place the DSP into a known good state out of power-up. The

RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core

and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be

held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages

should be at their proper operating conditions.

Table 4-1 assumes testing over recommended operating conditions.

Table 4-1. Reset Timing Requirements

NO. MIN MAX UNIT

1 t

w(RSTL)

Pulse width, RESET low 100 ns

2 t

su(BPV-RSTH)

Setup time, boot pins valid before RESET high 20 ns

3 t

h(RSTH-BPV)

Hold time, boot pins valid after RESET high 20 ns

Peripheral and Electrical Specifications38 Submit Documentation Feedback

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 113 114

Sin comentarios

Texas Instruments TMS320C6722 Manual de usuario Pagina 38