Texas Instruments TMS320C674X Manual de usuario Pagina 1

TMS320C674x/OMAP-L1x ProcessorEthernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) ModuleUser's GuideLiterature Number: SP

PrefaceSPRUFL5B–April 2011Read This FirstAbout This ManualThis document provides a functional description of the Ethernet Media Access Controller (EMA

EMAC Module Registerswww.ti.com5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)The MAC interrupt status (unmasked) register (MACINTSTATRA

www.ti.comEMAC Module Registers5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)The MAC interrupt mask set register (MACINTMASKSET) is shown in Fig

EMAC Module Registerswww.ti.com5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register(RXMBPENABLE)The receive multicast/broadcast/promis

www.ti.comEMAC Module RegistersTable 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)Field Descriptions (continued)Bi

EMAC Module Registerswww.ti.comTable 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)Field Descriptions (continued)Bi

www.ti.comEMAC Module Registers5.22 Receive Unicast Enable Set Register (RXUNICASTSET)The receive unicast enable set register (RXUNICASTSET) is shown

EMAC Module Registerswww.ti.com5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)The receive unicast clear register (RXUNICASTCLEAR) is shown in Fig

www.ti.comEMAC Module Registers5.24 Receive Maximum Length Register (RXMAXLEN)The receive maximum length register (RXMAXLEN) is shown in Figure 62 and

EMAC Module Registerswww.ti.com5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)The receive filter low priority frame thre

www.ti.comEMAC Module Registers5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER)The receive channel 0-7 free buffer count

www.ti.comRelated Documentation From Texas InstrumentsSPRUGM7 — OMAP-L138 Applications Processor System Reference Guide. Describes theSystem-on-Chip (

EMAC Module Registerswww.ti.com5.29 MAC Control Register (MACCONTROL)The MAC control register (MACCONTROL) is shown in Figure 67 and described in Tabl

www.ti.comEMAC Module RegistersTable 66. MAC Control Register (MACCONTROL) Field Descriptions (continued)Bit Field Value Description4 TXFLOWEN Transmi

EMAC Module Registerswww.ti.com5.30 MAC Status Register (MACSTATUS)The MAC status register (MACSTATUS) is shown in Figure 68 and described in Table 67

www.ti.comEMAC Module RegistersTable 67. MAC Status Register (MACSTATUS) Field Descriptions (continued)Bit Field Value Description15-12 RXERRCODE 0-Fh

EMAC Module Registerswww.ti.com5.31 Emulation Control Register (EMCONTROL)The emulation control register (EMCONTROL) is shown in Figure 69 and describ

www.ti.comEMAC Module Registers5.33 MAC Configuration Register (MACCONFIG)The MAC configuration register (MACCONFIG) is shown in Figure 71 and describ

EMAC Module Registerswww.ti.com5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)The MAC source address low bytes register (MACSRCADDRLO) is sh

www.ti.comEMAC Module Registers5.37 MAC Hash Address Register 1 (MACHASH1)The MAC hash registers allow group addressed frames to be accepted on the ba

EMAC Module Registerswww.ti.com5.39 Back Off Test Register (BOFFTEST)The back off test register (BOFFTEST) is shown in Figure 77 and described in Tabl

www.ti.comEMAC Module Registers5.41 Receive Pause Timer Register (RXPAUSE)The receive pause timer register (RXPAUSE) is shown in Figure 79 and describ

User's GuideSPRUFL5B–April 2011EMAC/MDIO Module1 IntroductionThis document provides a functional description of the Ethernet Media Access Control

EMAC Module Registerswww.ti.com5.43 MAC Address Low Bytes Register (MACADDRLO)The MAC address low bytes register used in address matching (MACADDRLO),

www.ti.comEMAC Module Registers5.44 MAC Address High Bytes Register (MACADDRHI)The MAC address high bytes register (MACADDRHI) is shown in Figure 82 a

EMAC Module Registerswww.ti.com5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP)The transmit channel 0-7 DMA head descriptor

www.ti.comEMAC Module Registers5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)The transmit channel 0-7 completion pointer register (T

EMAC Module Registerswww.ti.com5.50 Network Statistics RegistersThe EMAC has a set of statistics that record events associated with frame traffic. The

www.ti.comEMAC Module Registers5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)The total number of IEEE 802.3X pause frames received by the EMAC (

EMAC Module Registerswww.ti.com5.50.7 Receive Oversized Frames Register (RXOVERSIZED)The total number of oversized frames received on the EMAC. An ove

www.ti.comEMAC Module RegistersTo determine the number of receive frames discarded by the EMAC for any reason, sum the followingstatistics (promiscuou

EMAC Module Registerswww.ti.com5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES)The total number of good broadcast frames transmitted on the

www.ti.comEMAC Module Registers5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL)The total number of frames transmitted on the EMAC that

DMAMaster8KCPPIRAMInterruptCombinerC0C1C2ControlModuleEMACModuleMDIOModuleEMACInterruptsMDIOInterruptsInterruptsEMACSubSystemRegisterBusDMA BusMI

EMAC Module Registerswww.ti.com5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE)The total number of frames on the EMAC that experienced

www.ti.comEMAC Module Registers5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511)The total number of 256-byte to 511-byte fr

EMAC Module Registerswww.ti.com5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)The total number of frames received on the

www.ti.comAppendix A GlossaryBroadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet deviceson the local network. The

Appendix Awww.ti.comMulticast MAC Address— A class of MAC address that sends a packet to potentially more than onerecipient. A group address is specif

www.ti.comAppendix B Revision HistoryTable 88 lists the changes made since the previous version of this document.Table 88. Document Revision HistoryRe

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

Architecturewww.ti.com1.4 Industry Standard(s) Compliance StatementThe EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sen

MII_TXCLKMII_TXD[3−0]MII_TXENMII_COLMII_CRSMII_RXCLKMII_RXD[3−0]MII_RXDVMII_RXERMDIO_CLKMDIO_DPhysicallayerdevice(PHY)SystemcoreTransformer2.5 MHzor25

RMII_TXD[1-0]RMII_TXENRMII_MHZ_50_CLKRMII_RXD[1-0]RMII_CRS_DVRMII_RXERMDIO_CLKMDIO_DMDIOEMACPhysicalLayerDevice(PHY)Transformer50MHzRJ-45Architecture

Preamble SFD Destination Source Len Data7 1 6 6 2 46−1500 4FCSNumber of bytesLegend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC)www.ti.c

Architecturewww.ti.com2.4.2 Ethernet’s Multiple Access ProtocolNodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- wh

SOP | EOP 600 60pBufferpNextPacket A60 bytes0SOPFragment 1Packet B5121514pBufferpNext512 bytesEOP00−−−Packet BFragment 3500 bytes502pBuffer−−−500pNext

2SPRUFL5B–April 2011Submit Documentation Feedback© 2011, Texas Instruments Incorporated

Architecturewww.ti.com2.5.2 Transmit and Receive Descriptor QueuesThe EMAC module processes descriptors in linked lists as discussed in Section 2.5.1.

www.ti.comArchitecture2.5.3 Transmit and Receive EMAC InterruptsThe EMAC processes descriptors in linked list chains as discussed in Section 2.5.1, us

Architecturewww.ti.comFigure 7. Transmit Buffer Descriptor FormatWord 031 0Next Descriptor PointerWord 131 0Buffer PointerWord 231 16 15 0Buffer Offse

www.ti.comArchitecture2.5.4.1 Next Descriptor PointerThe next descriptor pointer points to the 32-bit word aligned memory address of the next buffer d

Architecturewww.ti.com2.5.4.7 End of Packet (EOP) FlagWhen set, this flag indicates that the descriptor points to a packet buffer that is last for a g

www.ti.comArchitecture2.5.5 Receive Buffer Descriptor FormatA receive (RX) buffer descriptor (Figure 8) is a contiguous block of four 32-bit data word

Architecturewww.ti.comExample 2. Receive Buffer Descriptor in C Structure Format/*// EMAC Descriptor//// The following is the format of a single buffe

www.ti.comArchitecture2.5.5.4 Buffer LengthThis 16-bit field is used for two purposes:• Before the descriptor is first placed on the receive queue by

Architecturewww.ti.com2.5.5.11 Pass CRC (PASSCRC) FlagThis flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-

Arbiter andbus switchesCPUDMA Controllers8K bytedescriptormemoryConfigurationregistersInterruptlogicInterruptsto CPUEMAC interruptsMDIO interruptsConf

Preface ... 101 Int

Architecturewww.ti.com2.6.3 Interrupt ControlInterrupt conditions generated by the EMAC and MDIO modules are combined into four interrupt signalsthat

EMACcontrolmoduleControlregistersand logicPHYmonitoringPeripheralclockMDIOclockgeneratorUSERINTMDIOinterfacepollingPHYMDCLKMDIOLINKINTConfiguration bu

Architecturewww.ti.com2.7.2 MDIO Module Operational OverviewThe MDIO module implements the 802.3 serial management interface to interrogate and contro

www.ti.comArchitecture2.7.2.1 Initializing the MDIO ModuleThe following steps are performed by the application software or device driver to initialize

Architecturewww.ti.com2.7.2.4 Example of MDIO Register Access CodeThe MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY c

Clock andreset logicReceiveDMA engineInterruptcontrollerTransmitDMA engineControlregistersConfiguration busEMACcontrolmoduleConfiguration busRAMStateF

Architecturewww.ti.com2.8.1.4 Transmit DMA EngineThe transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to theC

www.ti.comArchitectureThe EMAC module operates independently of the CPU. It is configured and controlled by its register setmapped into device memory.

Architecturewww.ti.comIn either case, receive flow control prevents frame reception by issuing the flow control appropriate for thecurrent mode of ope

www.ti.comArchitecture2.9.2 Data TransmissionThe EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to thetransmi

www.ti.com(C0RXIMAX-C2RXIMAX) ... 683.13 EMAC Control Module

Architecturewww.ti.com2.9.2.6 Transmit Flow ControlIncoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any furth

www.ti.comArchitecture2.10 Packet Receive Operation2.10.1 Receive DMA Host ConfigurationTo configure the receive DMA for operation the host must:• Ini

Architecturewww.ti.com2.10.4 Hardware Receive QOS SupportHardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Ide

www.ti.comArchitecture2.10.7 Receive Frame ClassificationReceived frames are proper (good) frames, if they are between 64 bytes and the value in the r

Architecturewww.ti.comTable 5. Receive Frame Treatment SummaryAddress Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment0 0 X X X No frames

www.ti.comArchitecture2.10.9 Receive OverrunThe types of receive overrun are:• FIFO start of frame overrun (FIFO_SOF)• FIFO middle of frame overrun (F

Architecturewww.ti.com2.11 Packet Transmit OperationThe transmit DMA is an eight channel interface. Priority between the eight queues may be either fi

www.ti.comArchitecture2.12 Receive and Transmit LatencyThe transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission o

Architecturewww.ti.com2.14 Reset Considerations2.14.1 Software Reset ConsiderationsPeripheral clock and reset control is done through the Power and Sl

www.ti.comArchitecture2.15 Initialization2.15.1 Enabling the EMAC/MDIO PeripheralWhen the device is powered on, the EMAC peripheral may be in a disabl

www.ti.com5.31 Emulation Control Register (EMCONTROL) ... 1145.32 FIFO Control Regi

Architecturewww.ti.com2.15.4 EMAC Module InitializationThe EMAC module is used to send and receive data packets over the network. This is done bymaint

www.ti.comArchitecture2.16 Interrupt Support2.16.1 EMAC Module Interrupt Events and RequestsThe EMAC module generates 26 interrupt events:• TXPENDn: T

Architecturewww.ti.comWhen the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing thepacket's last buffer desc

www.ti.comArchitectureThe receive host error conditions are:• Ownership bit not set in input buffer• Zero buffer pointerThe application software must

Architecturewww.ti.com2.16.2.2 User Access Completion InterruptWhen the GO bit in one of the MDIO register USERACCESS0 transitions from 1 to 0 (indica

www.ti.comArchitecture2.17 Power ManagementEach of the three main components of the EMAC peripheral can independently be placed inreduced-power modes

EMAC Control Module Registerswww.ti.com3 EMAC Control Module RegistersTable 8 lists the memory-mapped registers for the EMAC control module. See your

www.ti.comEMAC Control Module RegistersTable 8. EMAC Control Module Registers (continued)Offset Acronym Register Description Section70h C0RXIMAX EMAC

EMAC Control Module Registerswww.ti.com3.2 EMAC Control Module Software Reset Register (SOFTRESET)The EMAC Control Module Software Reset Register (SOF

www.ti.comEMAC Control Module Registers3.3 EMAC Control Module Interrupt Control Register (INTCONTROL)The EMAC control module interrupt control regist

www.ti.comList of Figures1 EMAC and MDIO Block Diagram... 132 Eth

EMAC Control Module Registerswww.ti.com3.4 EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers(C0RXTHRESHEN-C2RXTHRESHEN)T

www.ti.comEMAC Control Module Registers3.5 EMAC Control Module Interrupt Core Receive Interrupt Enable Registers(C0RXEN-C2RXEN)The EMAC control module

EMAC Control Module Registerswww.ti.com3.6 EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers(C0TXEN-C2TXEN)The EMAC control modul

www.ti.comEMAC Control Module Registers3.7 EMAC Control Module Interrupt Core Miscellaneous Interrupt Enable Registers(C0MISCEN-C2MISCEN)The EMAC cont

EMAC Control Module Registerswww.ti.com3.8 EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers(C0RXTHRESHSTAT-C2RXTHRESHST

www.ti.comEMAC Control Module Registers3.9 EMAC Control Module Interrupt Core Receive Interrupt Status Registers(C0RXSTAT-C2RXSTAT)The EMAC control mo

EMAC Control Module Registerswww.ti.com3.10 EMAC Control Module Interrupt Core Transmit Interrupt Status Registers(C0TXSTAT-C2TXSTAT)The EMAC control

www.ti.comEMAC Control Module Registers3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers(C0MISCSTAT-C2MISCSTAT)The EMAC

EMAC Control Module Registerswww.ti.com3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers(C0RXIMAX-C2RXIMAX)The EMAC

www.ti.comEMAC Control Module Registers3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers(C0TXIMAX-C2TXIMAX)The EMA

www.ti.com47 Transmit Interrupt Mask Set Register (TXINTMASKSET) ... 9248 Transmit Interrupt M

MDIO Registerswww.ti.com4 MDIO RegistersTable 22 lists the memory-mapped registers for the MDIO module. See your device-specific data manualfor the me

www.ti.comMDIO Registers4.2 MDIO Control Register (CONTROL)The MDIO control register (CONTROL) is shown in Figure 26 and described in Table 24.Figure

MDIO Registerswww.ti.com4.3 PHY Acknowledge Status Register (ALIVE)The PHY acknowledge status register (ALIVE) is shown in Figure 27 and described in

www.ti.comMDIO Registers4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)The MDIO link status change interrupt (unmasked) registe

MDIO Registerswww.ti.com4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)The MDIO link status change interrupt (masked) register

www.ti.comMDIO Registers4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)The MDIO user command complete interrupt (unmasked) r

MDIO Registerswww.ti.com4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)The MDIO user command complete interrupt (masked) re

www.ti.comMDIO Registers4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)The MDIO user command complete interrupt mask set r

MDIO Registerswww.ti.com4.10 MDIO User Command Complete Interrupt Mask Clear Register(USERINTMASKCLEAR)The MDIO user command complete interrupt mask c

www.ti.comMDIO Registers4.11 MDIO User Access Register 0 (USERACCESS0)The MDIO user access register 0 (USERACCESS0) is shown in Figure 35 and describe

www.ti.comList of Tables1 EMAC and MDIO Signals for MII Interface... 152 EMA

MDIO Registerswww.ti.com4.12 MDIO User PHY Select Register 0 (USERPHYSEL0)The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 36 and

www.ti.comMDIO Registers4.13 MDIO User Access Register 1 (USERACCESS1)The MDIO user access register 1 (USERACCESS1) is shown in Figure 37 and describe

MDIO Registerswww.ti.com4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 38 and

www.ti.comEMAC Module Registers5 EMAC Module RegistersTable 37 lists the memory-mapped registers for the EMAC. See your device-specific data manual fo

EMAC Module Registerswww.ti.comTable 37. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description Section164h

www.ti.comEMAC Module RegistersTable 37. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Register Description Section67Ch

EMAC Module Registerswww.ti.com5.1 Transmit Revision ID Register (TXREVID)The transmit revision ID register (TXREVID) is shown in Figure 39 and descri

www.ti.comEMAC Module Registers5.3 Transmit Teardown Register (TXTEARDOWN)The transmit teardown register (TXTEARDOWN) is shown in Figure 41 and descri

EMAC Module Registerswww.ti.com5.4 Receive Revision ID Register (RXREVID)The receive revision ID register (RXREVID) is shown in Figure 42 and describe

www.ti.comEMAC Module Registers5.6 Receive Teardown Register (RXTEARDOWN)The receive teardown register (RXTEARDOWN) is shown in Figure 44 and describe

www.ti.com46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ... 9247 Transmit Interrupt Mask

EMAC Module Registerswww.ti.com5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)The transmit interrupt status (unmasked) register (TXIN

www.ti.comEMAC Module Registers5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)The transmit interrupt status (masked) register (TXINT

EMAC Module Registerswww.ti.com5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)The transmit interrupt mask set register (TXINTMASKSET) is shown

www.ti.comEMAC Module Registers5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)The transmit interrupt mask clear register (TXINTMASKCLEAR)

EMAC Module Registerswww.ti.com5.11 MAC Input Vector Register (MACINVECTOR)The MAC input vector register (MACINVECTOR) is shown in Figure 49 and descr

www.ti.comEMAC Module Registers5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR)The MAC end of interrupt vector register (MACEOIVECTOR) is show

EMAC Module Registerswww.ti.com5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)The receive interrupt status (unmasked) register (RXINT

www.ti.comEMAC Module Registers5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)The receive interrupt status (masked) register (RXINTS

EMAC Module Registerswww.ti.com5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)The receive interrupt mask set register (RXINTMASKSET) is shown

www.ti.comEMAC Module Registers5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)The receive interrupt mask clear register (RXINTMASKCLEAR) i