Texas Instruments TMS320C67X/C67X+ DSP Manual de usuario Pagina 352
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Pipeline Execution of Instruction Types
Pipeline4-20 SPRU733
4.2.4 Load Instructions
Data loads require five, E1−E5, of the pipeline execute phases to complete
their operations (see Table 4−6). Figure 4−14 shows the fetch, decode, and
execute phases of the pipeline that the load instructions use.
Figure 4−15 shows the operations occurring in the pipeline phases for a load.
In the E1 phase, the data address pointer is modified in its register. In the E2
phase, the data address is sent to data memory. In the E3 phase, a memory
read at that address is performed.
Table 4−6. Load Instruction Execution
Pipeline Stage
E1 E2 E3 E4 E5
Read baseR
offsetR
Written baseR dst
Unit in use
.D
Figure 4−14. Load Instruction Phases
PG PS PW PR DP DC E1 E2 E3 E4 E5
4 delay slots
Address
modification
- TMS320C67x/C67x+ DSP 1
- CPU and Instruction Set 1
- Reference Guide 1
- Read This First 3
- Trademarks 4
- Contents 10
- Examples 17
- CPU Data Paths and Control 27
- 2.1 Introduction 28
- Data path A 29
- Data path B 29
- 2.4 Register File Cross Paths 32
- 2.6 Data Address Paths 33
- 2.7 Control Register File 33
- Control Register File 45
- Field Descriptions 50
- Instruction Set 61
- 3-9Instruction SetSPRU733 69
- (e−1023) 73
- 3.4 Delay Slots 74
- 3.5 Parallel Operations 76
- 3.5.1 Example Parallel Code 78
- 3.6 Conditional Operations 79
- 3.7 Resource Constraints 80
- Resource Constraints 81
- 3-21Instruction SetSPRU733 81
- Instruction Set3-22 SPRU733 82
- 3-23Instruction SetSPRU733 83
- Instruction Set3-24 SPRU733 84
- 3-25Instruction SetSPRU733 85
- Instruction Set3-26 SPRU733 86
- 3-27Instruction SetSPRU733 87
- Instruction Set3-28 SPRU733 88
- 3.8 Addressing Modes 90
- Addressing Modes 91
- 3-31Instruction SetSPRU733 91
- LDW .D1 *++A4[9],A1 91
- Instruction Set3-32 SPRU733 92
- ADDAH .D1 A4,A1,A4 92
- 3.9 Instruction Compatibility 94
- 3.10 Instruction Descriptions 94
- 3-35 Instruction SetSPRU733 95
- 3-37 Instruction SetSPRU733 97
- 3 1 5 5 1 1 1 100
- 3 1 5 5 5 1 7 1 1 104
- 3 1 5 5 5 6 1 1 106
- 31 29 28 27 23 22 76543210 119
- 3 1 5 16 1 1 119
- 3 1 5 5 5 1 1 1 125
- Bitwise AND 127
- AND Bitwise AND 128
- Branch Using a Displacement 129
- B Branch Using a Displacement 130
- Branch Using a Register 131
- B Branch Using a Register 132
- 3-73 Instruction SetSPRU733 133
- Instruction Type Branch 134
- Delay Slots 5 134
- Pipeline 134
- 3-75 Instruction SetSPRU733 135
- Clear a Bit Field 137
- CLR Clear a Bit Field 138
- Example 1 CLR .S1 A1,4,19,A2 139
- Example 2 CLR .S2 B1,B3,B2 139
- .unit = .L1 or .L2 146
- > src2) 1 → dst 147
- Example 1 CMPGT .L1X A1,B1,A2 148
- Example 2 CMPGT .L1X A1,B1,A2 148
- Example 3 CMPGT .L1 8,A1,A2 148
- Example 4 CMPGT .L1X A1,B1,A2 148
- Unsigned 32-bit integer 154
- < src2) 1 → dst 156
- Example 1 CMPLT .L1 A1,A2,A3 157
- Example 2 CMPLT .L1 A1,A2,A3 157
- Example 3 CMPLT .L1 9,A1,A2 157
- Floating-Point Value 166
- With Truncation 168
- 3 1 5 5 5 5 1 1 170
- Instruction Type Single-cycle 172
- Delay Slots 0 172
- See Also EXTU 172
- Example 1 EXT .S1 A1,10,19,A2 172
- Example 2 EXT .S1 A1,A2,A3 172
- See Also EXT 175
- Example 2 EXTU .S1 A1,A2,A3 175
- Example INTDPU .L1 A4,A1:A0 180
- Register Offset 183
- Example LDB .D1 *−A5[4],A7 185
- 3 1 5 15 1 3 1 1 186
- 3 1 5 5 5 4 1 1 1 188
- 3 1 5 5 5 4 1 3 1 1 191
- Example LDH .D1 *++A4[A1],A8 193
- Example 1 LDW .D1 *A10,B1 198
- Example 2 LDW .D1 *A4++[1],A6 198
- Example 3 LDW .D1 *++A4[1],A6 198
- 3-139 Instruction SetSPRU733 199
- Instruction Type Load 200
- Delay Slots 4 200
- See Also LDB, LDH 200
- Leftmost Bit Detection 201
- LMBD Leftmost Bit Detection 202
- Signed 16 LSB 203
- Example 1 MPY .M1 A1,A2,A3 204
- Example 2 MPY .M1 13,A1,A2 204
- Signed 16 MSB 207
- Example MPYH .M1 A1,A2,A3 208
- Example MPYHL .M1 A1,A2,A3 210
- Unsigned 16 LSB 211
- Unsigned 16 MSB 213
- 32-Bit Into 32-Bit Result 217
- Functional Unit 218
- See Also MPYID 218
- 32-Bit Into 64-Bit Result 219
- See Also MPYI 220
- Example MPYLH .M1 A1,A2,A3 222
- Double-Precision 228
- Double-Precision Result 230
- MPYSP2DP 230
- See Also MPY, MPYU, MPYUS 233
- Example MPYU .M1 A1,A2,A3 235
- Example MPYUS .M1 A1,A2,A3 237
- Syntax MV (.unit) src2, dst 238
- Opcode .L unit 238
- Opcode .S unit 238
- 3 1 5 5 1 1 239
- 3 1 5 5 1 6 1 1 240
- MVK .S1 0x00008000X, A0 243
- MVK .S1 0xFFFF8000, A0 243
- Instruction Type Single cycle 244
- See Also MVKH, MVKL, MVKLH 244
- Example 1 244
- Example 2 MVK .D2 14,B8 244
- MVKH/MVKLH 245
- MVKL 0x12345678 246
- MVKH 0x12345678 246
- MVKL label 246
- MVKH label 246
- 31 29 28 27 23 22 7 6543210 247
- 3 1 5 5 1 7 1 1 249
- NOP No Operation 250
- No Operation 250
- Example 1 NOP 251
- Example 2 MVK .S1 1,A1 251
- NORM Normalize Integer 252
- Normalize Integer 252
- NOT Bitwise NOT 254
- Bitwise NOT 254
- Bitwise OR 255
- OR Bitwise OR 256
- 3-207 Instruction SetSPRU733 267
- SADD .L1X B2,A5:A4,A7:A6 267
- 2 cycles after instruction 267
- SET Set a Bit Field 270
- Set a Bit Field 270
- Arithmetic Shift Left 273
- SHL Arithmetic Shift Left 274
- Arithmetic Shift Right 275
- SHR Arithmetic Shift Right 276
- Logical Shift Right 277
- SHRU Logical Shift Right 278
- src2) << 1) → dst 279
- Example SMPY .M1 A1,A2,A3 280
- Example SMPYHL .M1 A1,A2,A3 283
- Example SMPYLH .M1 A1,A2,A3 285
- Shift Left With Saturation 292
- 02E3 031Ch 293
- Written baseR 297
- 31 29 28 27 23 22 876 43210 298
- 3 1 5 15 1 1 1 298
- 3-243 Instruction SetSPRU733 303
- /B15, src 304
- Instruction Type Store 304
- See Also STB, STW 304
- 3-247 Instruction SetSPRU733 307
- See Also STB, STH 308
- 3 1 5 5 5 1 6 1 1 310
- Example SUBAW .D1 A5,2,A3 317
- << 1) + 1 → dst 318
- << 1 → dst 318
- Example 1 SUBC .L1 A0,A1,A0 319
- Example 2 SUBC .L1 A0,A1,A0 319
- XOR Bitwise Exclusive OR 330
- Bitwise Exclusive OR 330
- ZERO Zero a Register 332
- Zero a Register 332
- Figure 4−1. Pipeline Stages 334
- 4.1.1 Fetch 334
- 4.1.2 Decode 335
- 4.1.3 Execute 337
- Figure 4−5. Pipeline Phases 338
- 4.2.3 Store Instructions 350
- Written baseR dst 352
- LDW .D1 *A4++,A3 353
- 4.2.5 Branch Instructions 354
- 4.2.7 Four-Cycle Instructions 357
- 4.2.8 INTDP Instruction 358
- 4.2.9 DP Compare Instructions 359
- 4.2.11 MPYI Instruction 361
- 4.2.12 MPYID Instruction 362
- 4.2.13 MPYDP Instruction 363
- 4.2.14 MPYSPDP Instruction 364
- 4.2.15 MPYSP2DP Instruction 365
- 4.3.1 .S-Unit Constraints 366
- 4.3.2 .M-Unit Constraints 372
- 4.3.3 .L-Unit Constraints 380
- Performance Considerations 388
- Pipeline4-56 SPRU733 388
- 4.4.2 Multicycle NOPs 390
- Delay slots of the branch 391
- 4.4.3 Memory Considerations 392
- Program DC E1 E2 E3 393
- Pipeline4-62 SPRU733 394
- Interrupts 396
- 5.1 Overview 397
- Overview 400
- 5-5InterruptsSPRU733 400
- Interrupts5-6 SPRU733 401
- 5-7InterruptsSPRU733 402
- Located Outside the IST 403
- 5-11InterruptsSPRU733 406
- 5.3.2 Status of Interrupts 409
- 5-17InterruptsSPRU733 412
- If an execute 413
- 5-19InterruptsSPRU733 414
- 5.5.1 General Performance 416
- 5.5.2 Pipeline Interaction 416
- 5.6.2 Nested Interrupts 418
- 5.6.4 Traps 421
- Instruction Compatibility 422
- 3-126 424
- 3-134 424
- 3-139 424
- 3-238 426
- 3-243 426
- 3-247 426
- Appendix A 434
- Appendix C 434
- register offset 436
- mode r y op 1 0 s p 438
- y op 1 1 s p 438
- Appendix D 439
- D.3 32-Bit Opcode Maps 442
- Appendix E 443
- E.3 32-Bit Opcode Maps 446
- Appendix F 447
- F.3 32-Bit Opcode Maps 450
- Appendix G 452
- G.3 32-Bit Opcode Maps 454
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