Texas-instruments TMS320TCI6486 Manual de usuario descargar pdf (Pagina 114)

EMAC Port Registers

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5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 62 and described in

Table 56.

Figure 62. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

31 16

Reserved

R-0

15 2 1 0

HOST STAT

Reserved

MASK MASK

R-0 R/WC-0 R/WC-0

LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset

Table 56. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Reserved

1 HOSTMASK Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

0 STATMASK Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

114

C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010

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Texas-instruments TMS320TCI6486 Manual de usuario Pagina 114