Texas-instruments TMS320C6452 DSP Manual de usuario descargar pdf (Pagina 16)

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2.4.4 Deactivation (DCAB and DEAC)

DCAB

DDR_CLK

DDR_CLK

DDR_CS

DDR_CKE

DDR_RAS

DDR_WE

DDR_DQM[3:0]

DDR_CAS

DDR_BA[2:0]

DDR_A[13:11, 9:0]

DDR_A[10]

DEAC

DDR_CLK

DDR_CLK

DDR_CS

DDR_CKE

DDR_RAS

DDR_WE

DDR_DQM[3:0]

DDR_CAS

DDR_BA[2:0]

DDR_A[13:11, 9:0]

DDR_A[10]

Peripheral Architecture

The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or

following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and

mode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high to

ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command.

Figure 6. DCAB Command

The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 shows

the timings diagram for a DEAC command.

Figure 7. DEAC Command

DSP DDR2 Memory Controller16 SPRUF85 – October 2007

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