Texas-instruments TMS320C6452 DSP Manual de usuario descargar pdf (Pagina 31)

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DDR_CLK

DDR_CKE

DDR_CS

DDR_WE

DDR_RAS

DDR_CAS

DDR_DQM0

DDR_DQM1

DDR_DQS0

DDR_DQS1

DDR_BA[2:0]

DDR_A[13:0]

DDR_D[15:0]

DDR_VREF

DDR_ODT0

DDR_DQS0

DDR_DQS1

CKE

RAS

CAS

LDM

UDM

LDQS

UDQS

BA[2:0]

A[12:0]

DQ[15:0]

ODT

VREF

LDQS

UDQS

DDR2

memory

x16−bit

VREF

DDR2

memory

controller

DDR_ODT1

DDR_DQGATE0

(A)

DDR_DQGATE1

(A)

DDR_DQGATE2

(A)

DDR_DQGATE3

(A)

Using the DDR2 Memory Controller

Figure 18. Connecting to a Single 16-Bit DDR2 SDRAM Device

A These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data

manual.

SPRUF85 – October 2007 DSP DDR2 Memory Controller 31

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User's Guide 1
2 SPRUF85 – October 2007 2
Submit Documentation Feedback 2
Contents 3
Read This First 6
DSP DDR2 Memory Controller 9
Introduction 10
2 Peripheral Architecture 11
2.1 Clock Control 11
2.2 Memory Map 11
2.3 Signal Descriptions 11
Peripheral Architecture 12
2.4 Protocol Description(s) 13
D0 D1 D2 D3 D4 D5 D6 D7 17
2.6 Address Mapping 19
2.8 Refresh Scheduling 25
2.9 Self-Refresh Mode 26
2.10 Reset Considerations 26
2.12 Interrupt Support 28
2.13 EDMA Event Support 28
2.14 Emulation Considerations 28
IMPORTANT NOTICE 46

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