Texas Instruments TMS320C6457 Manual de usuario

TMS320C6457 DSPTurbo-Decoder Coprocessor 2 (TCP2)User's GuideLiterature Number: SPRUGK1March 2009

2 Introductionz−1z−1z−1BAXz−1z−1z−1B’A’X’InterleaverPunctureandrepetitionXP1P2P3InformationSwitches in upper position for information bits and in lowe

MAP1MAP2Received systematicsInterleaveDeinterleaveA prioriInterleaveA prioriReceived systematicsReceived paritiesReceived parities A’ & B ’ symbol

32-bit configuration bus64-bit EDMA3 busTurbo-decoder coprocessor (TCP2)REVT/XEVTgenerationCPUinterruptgenerationTCP2 controlEDMA3 I/F unit Memory blo

Parity AParity A’Parity BParity B’Void inputIII−1Apriori 1Apriori 2SystematicStop?(stoppingcriterionalgo)NewaprioriPrevious aprioriYesSystematicNoSlic

Standalone (SA) Modewww.ti.comFigure 5. Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/463:62 61:56 55:50 49:44 43:38 37:32 31:30 29:24 23

www.ti.comStandalone (SA) ModeFigure 11. EN = 0 (Big-Endian Mode) Rate = 1/4Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5B0' 0 B0 A0 X0

4.1.2 Interleaver Indexes4.2 Output Decision Data Format4.3 Stopping CriteriaStandalone (SA) Modewww.ti.comFigure 15. Rate 3/4 EN = 0 (Big-Endian Mode

4.4 Stopping Test Unit4.4.1 SNR Threshold Termination4.4.2 CRC Terminationwww.ti.comStandalone (SA) ModeThe CRC-based stopping criterion can be used b

4.4.3 Parameter Termination4.4.3.1 Maximum Iterations4.4.3.2 Minimum Iterations5 Shared-Processing (SP) ModeShared-Processing (SP) Modewww.ti.comThe C

MAPdecoderunitA for MAP 1and A’ for MAP2B for MAP1and B’ for MAP2(only rate 1/4)X for MAP1or X’ for MAP2EXT1: extrinsics after MAP1EXT2: extrinsics af

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NumSubframe+ CEILǒSizeBlockSizeMAX_SubframeǓSizeSubframe+ CEILǒSizeBlock256 NumSubframeǓ 256whileǒSizeBlocku SizeMAX_SubsystemǓ{SizeBlock+ SizeBloc

www.ti.comShared-Processing (SP) ModeEach sub-frame is independent of each other. There are three types of sub-frames. The first sub-framestarts the t

MAPdecoderunitMAP 1: Parity A orMAP 2: Parity A’MAP 2: Parity B’MAP 1: Parity B orVoid inputMAP 1: Systemic orMAP 2: Interleaved(systematic)MAP 1: De−

www.ti.comShared-Processing (SP) ModeFigure 23. EN = 1 (Little-Endian Mode) Rate = 1/3Word WordN + 1 NSP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP00 A1&apos

5.1.2 A Priori Data5.2 Output Data FormatShared-Processing (SP) Modewww.ti.comFigure 28. EN = 0 (Big-Endian Mode) Rate = 1/5Word WordN N + 1SP4 SP3 SP

6 Registerswww.ti.comRegistersThe TCP2 contains several memory-mapped registers accessible via the CPU, QDMA, and EDMA3. Aperipheral-bus access is fas

Registerswww.ti.comTable 4. TCP2 RAMs (continued)TCP2 Data Offset Register/MemoryAddress Abbreviation Name Address Range Length0xA0000 B0 Beta Prolog

6.1 Peripheral Identification Register (PID)www.ti.comRegistersThe peripheral identification register (PID) is a constant register that contains the I

6.2 TCP2 Input Configuration Register 0 (TCPIC0)Registerswww.ti.comThe TCP2 input configuration register 0 (TCPIC0) is shown in Figure 33 and describe

6.3 TCP2 Input Configuration Register 1 (TCPIC1)6.4 TCP2 Input Configuration Register 2 (TCPIC2)www.ti.comRegistersThe TCP2 input configuration regist

ContentsPreface ...

6.5 TCP2 Input Configuration Register 3 (TCPIC3)Registerswww.ti.comThe TCP2 input configuration register 3 (TCPIC3) is shown in Figure 36 and describe

6.6 TCP2 Input Configuration Register 4 (TCPIC4)www.ti.comRegistersThe TCP2 input configuration register 4 (TCPIC4) is shown in Figure 37 and describe

6.7 TCP2 Input Configuration Register 5 (TCPIC5)6.8 Tail SymbolsRegisterswww.ti.comThe TCP2 input configuration register 5 (TCPIC5) is shown in Figure

6.9 TCP2 Input Configuration Register 6 (TCPIC6)www.ti.comRegistersThe TCP2 input configuration register 6 (TCPIC6) is shown in Figure 39 and describe

6.10 TCP2 Input Configuration Register 7 (TCPIC7)Registerswww.ti.comThe TCP2 input configuration register 7 (TCPIC7) is shown in Figure 40 and describ

6.11 TCP2 Input Configuration Register 8 (TCPIC8)www.ti.comRegistersThe TCP2 input configuration register 8 (TCPIC8) is shown in Figure 41 and describ

6.12 TCP2 Input Configuration Register 9 (TCPIC9)Registerswww.ti.comThe TCP2 input configuration register 9 (TCPIC9) is shown in Figure 42 and describ

6.13 TCP2 Input Configuration Register 10 (TCPIC10)6.14 TCP2 Input Configuration Register 11 (TCPIC11)www.ti.comRegistersThe TCP2 input configuration

Registerswww.ti.comFigure 44. TCP2 Input Configuration Register 11 (TCPIC11)31 18 17 0Reserved TAIL6R/W-0 R/W-0LEGEND: R/W = Read/Write; R = Read only

6.15 TCP2 Input Configuration Register 12 (TCPIC12)6.16 TCP2 Input Configuration Register 13 (TCPIC13)www.ti.comRegistersThe TCP2 input configuration

www.ti.com8 Architecture ... 598.1

6.17 TCP2 Input Configuration Register 14 (TCPIC14)Registerswww.ti.comThe TCP2 input configuration register 14 (TCPIC14) is shown in Figure 47 and des

6.18 TCP2 Input Configuration Register 15 (TCPIC15)www.ti.comRegistersThe TCP2 input configuration register 15 (TCPIC15) is shown in Figure 48 and des

6.19 TCP2 Output Parameter Register 0 (TCPOUT0)6.20 TCP2 Output Parameter Register 1 (TCPOUT1)Registerswww.ti.comThe TCP2 output parameter register 0

6.21 TCP2 Output Parameter Register 2 (TCPOUT2)6.22 TCP2 Execution Register (TCPEXE)www.ti.comRegistersThe TCP2 output parameter register 2 (TCPOUT2)

6.23 TCP2 Endian Register (TCPEND)Registerswww.ti.comThe TCP2 endian register (TCPEND) is shown in Figure 53 and described in Table 28 . TCPEND should

6.24 TCP2 Error Register (TCPERR)www.ti.comRegistersThe TCP2 error register (TCPERR) is shown in Figure 54 and described in Table 29 . In case of an e

Registerswww.ti.comTable 29. TCP2 Error Register (TCPERR) Field Descriptions (continued)Bit Field Value Description4 SF Subframe length.0 No error1 Su

6.25 TCP2 Status Register (TCPSTAT)www.ti.comRegistersThe TCP2 status register (TCPSTAT) is shown in Figure 55 and described in Table 30 .Figure 55. T

Registerswww.ti.comTable 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued)Bit Field Value Description7 REXT Defines if the TCP2 is wai

6.26 TCP2 Emulation Register (TCPEMU)www.ti.comRegistersIn emulation mode, the access to TCP2 memories can be done in read or write. TCP2 supports emu

www.ti.comList of Figures1 3GPP and IS2000 Turbo-Encoder Block Diagram ... 102 3GPP

7 Endianness7.1 Data Memory for SystematicEndiannesswww.ti.comThe TCP2 is halted (or paused) after processing the ongoing frame. Any current frame pro

www.ti.comEndiannessFigure 61. Data Memory63:62 61:56 55:50 49:44 43:38 37:32 31:30 29:24 23:18 17:12 11:6 5:0RSVD SP9 SP8 SP7 SP6 SP5 RSVD SP4 SP3 SP

Endiannesswww.ti.comFigure 67. EN = 0 (Big-Endian Mode) Rate = 1/4Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5B0' 0 B0 A0 X0 B1'

7.1.1 Hard Decision Datawww.ti.comEndiannessFigure 71. EN = 0 (Big-Endian Mode) Rate = 3/4Word WordN N + 1SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP50 0 0

7.1.2 TCP_ENDIAN Register for Endianness ManagerEndiannesswww.ti.comFigure 77. Destination of Endianness Manager (OUT_ORDER = 0)63 62 32 31 1 0Stage S

7.1.3 Interleaver Data7.1.3.1 ENDIAN_INTR = 1www.ti.comEndiannessFigure 82. TCP_ENDIAN Register31 16ReservedR/W15 2 1 0ENDIAN_ ENDIAN_ReservedEXTR INT

INTER0INTER1INTER3INTER2Base 0Base 2Base 4Base 6INTER2INTER3INTER1INTER0EDMA363 0INTER3INTER2INTER1INTER0Kernel63 0TCPMemoryEndian_Intr=1Endiannessman

7.1.4 Extrinsic Data7.1.4.1 ENDIAN_EXTR = 1XT0XT1XT2XT3XT4XT6XT7XT5Base 0Base 7Endian_Extr=1XT7XT6XT5XT4XT0XT2XT3XT1EndiannessmanagerXT7XT6XT5XT4XT3XT

Endiannesswww.ti.comFigure 90. Data Source - Kernel (ENDIAN_EXTR = 1)63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EX

7.1.4.2 ENDIAN_EXTR = 0XT3XT2XT1XT0XT7XT5XT4XT6Base 0Base 7Endian_Extr=0XT7XT6XT5XT4XT0XT2XT3XT1EndiannessmanagerXT7XT6XT5XT4XT3XT2XT1XT063 0 63 0EDMA

www.ti.com53 TCP2 Endian Register (TCPEND) ... 4454 TCP2 Error Reg

BetamemoryBetamemoryScratchAlphaExtrinsicExtrinsicsignalsDatafrommemory8.1 Sub-block and Sliding Window SegmentationArchitecturewww.ti.comFigure 95. M

Subblock : 1, 2 or 4 sliding windowsFrame or subframe (length < 5114)First subblockMiddle subblockMiddle subblockMiddle subblockLast subblockBetaPr

Shared-processing frame (length > 20730)First subframeMiddle subframeMiddle subframeMiddle subframeLast subframePrologMust point tovalid addressTai

RMAX+ 128whileǒǒNSB R NSW* NǓw(R * 48)ǓR +WIN_SIZENSBIFǒR NSBt WIN_SIZEǓR ) )if(N v 128)NSW + 1, R + NELSENSW + 2IFǒNSW+ 2Ǔ{{WIN_SIZE + CEILƪNńNS

8.4.2 Input Sign8.4.3 Log Equation8.4.4 Re-Encode9 ProgrammingProgrammingwww.ti.comThe TCP assumes that the encoded bits are converted into signed bin

9.1 EDMA3 Resources9.1.1 TCP2 Dedicated EDMA3 Resources9.1.2 Special TCP2 EDMA3 Programming Considerationswww.ti.comProgrammingNote that several user

9.2 Programming Standalone (SA) Mode9.2.1 EDMA3 Programming9.2.1.1 Input Configuration Parameters Transfer9.2.1.2 Systematics and Parities TransferPro

9.2.1.3 Interleaver Indexes Transferwww.ti.comProgramming– TCINTEN = 0 (Transfer complete interrupt is disabled)– TCC = 1 to 63 (Transfer Complete Cod

9.2.1.4 Hard-Decisions TransferProgrammingwww.ti.com• SRCBIDX = 0 (Source 2nd Dimension Index)• DSTBIDX = 0 (Destination 2nd Dimension Index• SRCCIDX

9.2.1.5 Output Parameters Transfer9.2.2 Input Configurations Parameters Programmingwww.ti.comProgramming3. Null EDMA3 transfer parameters (with all ze

www.ti.comList of Tables1 Frame Sizes for Standalone (SA) Mode and Shared-Processing (SP) Mode ... 122 Interleaver

9.3 Programming Shared-Processing (SP) ModeProgrammingwww.ti.comThe minimum number of iterations (MINIT bits in TCPIC3) should be selected as a functi

9.3.1 EDMA3 Programming9.3.1.1 Input Configuration Parameters Transfer9.3.1.2 Systematics and Parities Transferwww.ti.comProgrammingThis EDMA3 transfe

9.3.1.3 A Priori TransferProgrammingwww.ti.com• Word count = 2 * ceil (frame_length/2)• BCNT = (Word count /2) (No of arrays of length ACNT)• DESTINAT

9.3.1.4 Extrinsics Transfer9.3.2 Input Configurations Parameters Programmingwww.ti.comProgramming1. The EDMA3 input configuration parameters transfer

10 Output Parameters11 Events GenerationWrite toTCPENDWrite toTCPEXESoftresetXEVTWriteinputparamsXEVT XEVTWriteinputdata coefficientsinterleaverWriteM

Input configparamsSyst&ParSF1 SF1ExtrinsicsTCP processingTCPXEVT TCPXEVT TCPREVT TCPXEVTMAP1TCP processingTCPXEVTInput configparamsTCPXEVT TCPREVT

13.1.2 Unexpected Frame Length: F13.1.3 Unexpected Prolog Length: P13.1.4 Unexpected Subframe Length: SF13.1.5 Unexpected Reliability Length: R13.1.6

13.1.10 Unexpected Max and Min Iterations: MAXMINITER13.2 Status13.2.1 TCP2 Decoder Status: dec_busy13.2.2 TCP2 Stopped Due to Error: ERR13.2.3 TCP2 W

13.2.12 TCP2 Active State Status: Active_state13.2.13 TCP2 Active Iteration Status: Active_iter13.2.14 TCP2 SNR Status: snr_exceed13.2.15 TCP2 CRC Sta

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

PrefaceSPRUGK1 – March 2009Read This FirstAbout This ManualChannel decoding of high bit-rate data channels found in third-generation (3G) cellular sta

1 FeaturesUser's GuideSPRUGK1 – March 2009TMS320C6457 Turbo-Decoder Coprocessor 2Channel decoding of high bit-rate data channels found in third-g