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Y/C Video Display Mode
Video Display Port4-18 SPRU629
The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are
unpacked from each word as shown in Figure 4–16.
Figure 4–16. 8-Bit Y/C FIFO Unpacking
Y FIFO
Cb FIFO
Y 2 Y 4 Y 6Y 1 Y 3 Y 5 Y 7
VDOUT[9–2]
VCLKOUT
63 5655 4847 4039 32
Y 21 Y 20Y 23 Y 22
Y 29 Y 28Y 31 Y 30
Y 5 Y 4Y 7 Y 6
Y 13 Y 12Y 15 Y 14
Cb 5 Cb 4Cb 7 Cb 6
Cb 13 Cb 12Cb 15 Cb 14
Cr FIFO
Little-Endian Unpacking
Y 8 Y 10Y 9 Y 11
Cb 0 Cb 1 Cb 2 Cb 3Cr 0 Cr 1 Cr 2 Cr 3
VDOUT[19–12]
Cb 4 Cb 5Cr 4 Cr 5
Y 0
31 2423 1615 8 7 0
Y 17 Y 16Y 19 Y 18
Y 25 Y 24Y 27 Y 26
Y 1 Y 0Y 3 Y 2
Y 9 Y 8Y 11 Y 10
31 2423 1615 8 7 0
Cb 1 Cb 0Cb 3 Cb 2
Cb 9 Cb 8Cb 11 Cb 10
31 2423 1615 8 7 0
63 5655 4847 4039 32
63 5655 4847 4039 32
Cr 5 Cr 4Cr 7 Cr 6
Cr 13 Cr 12Cr 15 Cr 14
Cr 1 Cr 0Cr 3 Cr 2
Cr 9 Cr 8Cr 11 Cr 10
Y FIFO
Cb FIFO
63 5655 4847 4039 32
Y 21Y 20 Y 23Y 22
Y 29Y 28 Y 31Y 30
Y 5Y 4 Y 7Y 6
Y 13Y 12 Y 15Y 14
Cb 5Cb 4 Cb 7Cb 6
Cb 13Cb 12 Cb 15Cb 14
Cr FIFO
Big-Endian Unpacking
31 2423 1615 8 7 0
Y 17Y 16 Y 19Y 18
Y 25Y 24 Y 27Y 26
Y 1Y 0 Y 3Y 2
Y 9Y 8 Y 11Y 10
31 2423 1615 8 7 0
Cb 1Cb 0 Cb 3Cb 2
Cb 9Cb 8 Cb 11Cb 10
31 2423 1615 8 7 0
63 5655 4847 4039 32
63 5655 4847 4039 32
Cr 5Cr 4 Cr 7Cr 6
Cr 13Cr 12 Cr 15Cr 14
Cr 1Cr 0 Cr 3Cr 2
Cr 9Cr 8 Cr 11Cr 10
- TMS320C64x DSP 1
- Reference Guide 1
- Read This First 3
- Trademarks 4
- Contents 10
- Overview 18
- 1.1 Video Port 19
- Video Port 20
- 1-3OverviewSPRU629 20
- 1.2 Video Port FIFO 22
- 1.3 Video Port Registers 29
- 1.4 Video Port Pin Mapping 30
- 2.1 Reset Operation 35
- 2.1.3 Software Port Reset 36
- 2.1.4 Capture Channel Reset 36
- 2.1.5 Display Channel Reset 37
- 2.2 Interrupt Operation 38
- 2.3 DMA Operation 39
- DMA Operation 41
- Video Port2-8 SPRU629 41
- 2-9Video PortSPRU629 42
- Video Port2-10 SPRU629 43
- 2.3.4 DMA Interface Operation 44
- 2.4 Clocks 45
- 2.5.2 FIFO Size 46
- Table 2–8 54
- Video Capture Port 63
- 3.2 BT.656 Video Capture Mode 65
- 3.2.4 BT.656 Data Sampling 70
- 3.2.5 BT.656 FIFO Packing 71
- BT.656 Video Capture Mode 72
- 3-11Video Capture PortSPRU629 73
- 3.3 Y/C Video Capture Mode 74
- Y/C Video Capture Mode 75
- 3-13Video Capture PortSPRU629 75
- 3.3.4 Y/C FIFO Packing 76
- 3-15Video Capture PortSPRU629 77
- 3-17Video Capture PortSPRU629 79
- 3-21Video Capture PortSPRU629 83
- 3-23Video Capture PortSPRU629 85
- 3.4.4 Field Identification 86
- 3-25Video Capture PortSPRU629 87
- 3.5 Video Input Filtering 88
- 3.5.3 Scaling Operation 89
- 3.5.4 Edge Pixel Replication 91
- 3.6 Ancillary Data Capture 93
- 3.7 Raw Data Capture Mode 94
- 3.7.2 Raw Data FIFO Packing 95
- Raw Data Capture Mode 96
- 3-35Video Capture PortSPRU629 97
- Figure 3–21 98
- 3.8 TSI Capture Mode 99
- 3.8.6 Writing to the FIFO 103
- Figure 3–25. TSI FIFO Packing 103
- 3.8.7 Reading from the FIFO 104
- YDEF YDEFYDEF YDEF 105
- CbDEF CbDEFCrDEF CrDEF 105
- 3.13 Video Capture Registers 111
- Field Descriptions 113
- Video Capture Registers 127
- 3-65Video Capture PortSPRU629 127
- Video Display Port 146
- 4.1.1 Image Timing 147
- 4.1.2 Video Display Counters 150
- 4.1.3 Sync Signal Generation 152
- 4.1.4 External Sync Operation 153
- 4.1.5 Port Sync Operation 153
- 4.2 BT.656 Video Display Mode 154
- 4.2.2 Blanking Codes 157
- 4.2.3 BT.656 Image Display 157
- 4.2.4 BT.656 FIFO Unpacking 158
- BT.656 Video Display Mode 159
- 4-15Video Display PortSPRU629 160
- 4.3 Y/C Video Display Mode 161
- 4.3.2 Y/C Blanking Codes 162
- 4.3.3 Y/C Image Display 162
- 4.3.4 Y/C FIFO Unpacking 162
- Y/C Video Display Mode 163
- 4-19Video Display PortSPRU629 164
- 4.4 Video Output Filtering 166
- 4.4.3 Scaling Operation 167
- 4.4.4 Edge Pixel Replication 168
- Video Output Filtering 169
- 4.5 Ancillary Data Display 170
- 4.6 Raw Data Display Mode 170
- 4.6.2 Raw Data FIFO Unpacking 171
- Raw Data Display Mode 172
- 4-27Video Display PortSPRU629 172
- 4-29Video Display PortSPRU629 174
- 4-33Video Display PortSPRU629 178
- 4.9 Display Timing Examples 180
- Display Timing Examples 181
- 4-36 Video Display Port 181
- 4-37Video Display PortSPRU629 182
- VDTHRLD with a value of 3 184
- 4-40 Video Display Port 185
- 4-41Video Display PortSPRU629 186
- 4-43Video Display PortSPRU629 188
- 4-44 Video Display Port 189
- 4-45Video Display PortSPRU629 190
- 4-47Video Display PortSPRU629 192
- 4-49Video Display PortSPRU629 194
- 4-51Video Display PortSPRU629 196
- 4.12 Video Display Registers 197
- General Purpose I/O Operation 242
- 5.1 GPIO Registers 243
- Chapter 6 268
- 6.1 Overview 269
- 6.2 Interface 270
- 6.3 Operational Details 270
- 6.4 Enabling VIC Port 272
- 6.5 VIC Port Registers 272
- Table 6–4 273
- Appendix A 277
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