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Displaying Video in Raw Data Mode
4-49Video Display PortSPRU629
22) If continuous display is enabled, the video port begins displaying again at
the start of the next field or frame. If noncontinuous field 1 and field 2 or
frame display is enabled, the next field or frame is displayed, during which
the DSP must clear the appropriate completion status bit or a DCNA
interrupt occurs and incorrect data may be output.
4.11 Displaying Video in Raw Data Mode
In order to display video in the raw data mode, the following steps are needed:
1) Set the frame size in VDFRMSZ. Set the number of lines per frame
(FRMHIGHT) and the number of pixels per line (FRMWIDTH).
2) Set the horizontal blanking in VDHBLNK. Specify the frame pixel counter
value where horizontal blanking starts (HBLNKSTART) and pixel location
where horizontal blanking stops (HBLNKSTOP).
3) Set the vertical blanking start for field 1 in VDVBLKS1. Specify the frame
line (VBLNKYSTART1) and frame pixel counter (VBLNKXSTART1) values
for the pixel where vertical blanking starts for field 1.
4) Set the vertical blanking end for field 1 in VDVBLKE1. Specify the frame
line (VBLNKYSTOP1) and frame pixel counter (VBLNKXSTOP1) values
for the pixel where vertical blanking ends for field 1.
5) Set the vertical blanking start for field 2 in VDVBLKS2. Specify the frame
line (VBLNKYSTART2) and frame pixel counter (VBLNKXSTART2) values
for the pixel where vertical blanking starts for field 2.
6) Set the vertical blanking end for field 2 in VDVBLKE2. Specify the frame
line (VBLNKYSTOP2) and frame pixel counter (VBLNKXSTOP2) values
for the pixel where vertical blanking ends for field 2.
7) Set the vertical synchronization start for field 1 in VDVSYNS1. Specify the
frame line (VSYNCYSTART1) and frame pixel counter (VSYNCXSTART1)
values for the pixel where vertical synchronization starts for field 1.
8) Set the vertical synchronization end for field 1 in VDVSYNE1. Specify the
frame line (VSYNCYSTOP1) and frame pixel counter (VSYNCXSTOP1)
values for the pixel where vertical synchronization ends for field 1.
9) Set the vertical synchronization start for field 2 in VDVSYNS2. Specify the
frame line (VSYNCYSTART2) and frame pixel counter (VSYNCXSTART2)
values for the pixel where vertical synchronization starts for field 2.
10) Set the vertical synchronization end for field 2 in VDVSYNE2. Specify the
frame line (VSYNCYSTOP2) and frame pixel counter (VSYNCXSTOP2)
values for the pixel where vertical synchronization ends for field 2.
- TMS320C64x DSP 1
- Reference Guide 1
- Read This First 3
- Trademarks 4
- Contents 10
- Overview 18
- 1.1 Video Port 19
- Video Port 20
- 1-3OverviewSPRU629 20
- 1.2 Video Port FIFO 22
- 1.3 Video Port Registers 29
- 1.4 Video Port Pin Mapping 30
- 2.1 Reset Operation 35
- 2.1.3 Software Port Reset 36
- 2.1.4 Capture Channel Reset 36
- 2.1.5 Display Channel Reset 37
- 2.2 Interrupt Operation 38
- 2.3 DMA Operation 39
- DMA Operation 41
- Video Port2-8 SPRU629 41
- 2-9Video PortSPRU629 42
- Video Port2-10 SPRU629 43
- 2.3.4 DMA Interface Operation 44
- 2.4 Clocks 45
- 2.5.2 FIFO Size 46
- Table 2–8 54
- Video Capture Port 63
- 3.2 BT.656 Video Capture Mode 65
- 3.2.4 BT.656 Data Sampling 70
- 3.2.5 BT.656 FIFO Packing 71
- BT.656 Video Capture Mode 72
- 3-11Video Capture PortSPRU629 73
- 3.3 Y/C Video Capture Mode 74
- Y/C Video Capture Mode 75
- 3-13Video Capture PortSPRU629 75
- 3.3.4 Y/C FIFO Packing 76
- 3-15Video Capture PortSPRU629 77
- 3-17Video Capture PortSPRU629 79
- 3-21Video Capture PortSPRU629 83
- 3-23Video Capture PortSPRU629 85
- 3.4.4 Field Identification 86
- 3-25Video Capture PortSPRU629 87
- 3.5 Video Input Filtering 88
- 3.5.3 Scaling Operation 89
- 3.5.4 Edge Pixel Replication 91
- 3.6 Ancillary Data Capture 93
- 3.7 Raw Data Capture Mode 94
- 3.7.2 Raw Data FIFO Packing 95
- Raw Data Capture Mode 96
- 3-35Video Capture PortSPRU629 97
- Figure 3–21 98
- 3.8 TSI Capture Mode 99
- 3.8.6 Writing to the FIFO 103
- Figure 3–25. TSI FIFO Packing 103
- 3.8.7 Reading from the FIFO 104
- YDEF YDEFYDEF YDEF 105
- CbDEF CbDEFCrDEF CrDEF 105
- 3.13 Video Capture Registers 111
- Field Descriptions 113
- Video Capture Registers 127
- 3-65Video Capture PortSPRU629 127
- Video Display Port 146
- 4.1.1 Image Timing 147
- 4.1.2 Video Display Counters 150
- 4.1.3 Sync Signal Generation 152
- 4.1.4 External Sync Operation 153
- 4.1.5 Port Sync Operation 153
- 4.2 BT.656 Video Display Mode 154
- 4.2.2 Blanking Codes 157
- 4.2.3 BT.656 Image Display 157
- 4.2.4 BT.656 FIFO Unpacking 158
- BT.656 Video Display Mode 159
- 4-15Video Display PortSPRU629 160
- 4.3 Y/C Video Display Mode 161
- 4.3.2 Y/C Blanking Codes 162
- 4.3.3 Y/C Image Display 162
- 4.3.4 Y/C FIFO Unpacking 162
- Y/C Video Display Mode 163
- 4-19Video Display PortSPRU629 164
- 4.4 Video Output Filtering 166
- 4.4.3 Scaling Operation 167
- 4.4.4 Edge Pixel Replication 168
- Video Output Filtering 169
- 4.5 Ancillary Data Display 170
- 4.6 Raw Data Display Mode 170
- 4.6.2 Raw Data FIFO Unpacking 171
- Raw Data Display Mode 172
- 4-27Video Display PortSPRU629 172
- 4-29Video Display PortSPRU629 174
- 4-33Video Display PortSPRU629 178
- 4.9 Display Timing Examples 180
- Display Timing Examples 181
- 4-36 Video Display Port 181
- 4-37Video Display PortSPRU629 182
- VDTHRLD with a value of 3 184
- 4-40 Video Display Port 185
- 4-41Video Display PortSPRU629 186
- 4-43Video Display PortSPRU629 188
- 4-44 Video Display Port 189
- 4-45Video Display PortSPRU629 190
- 4-47Video Display PortSPRU629 192
- 4-49Video Display PortSPRU629 194
- 4-51Video Display PortSPRU629 196
- 4.12 Video Display Registers 197
- General Purpose I/O Operation 242
- 5.1 GPIO Registers 243
- Chapter 6 268
- 6.1 Overview 269
- 6.2 Interface 270
- 6.3 Operational Details 270
- 6.4 Enabling VIC Port 272
- 6.5 VIC Port Registers 272
- Table 6–4 273
- Appendix A 277
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