Texas-instruments TMS320C3x Manual de usuario Pagina 257
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DP read
DP written
Resolving Register Conflicts
8-21
Pipeline Operation
Example 8–16. Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict
LDP TABLE_ADDR
POP R0
LDF *–AR3(2),R1
LDI @TABLE_ADDR,AR0
PUSHF R6
PUSH R4
Pipeline Operation
PC Fetch
Decode Read Execute
n LDP — — —
n+1 POP LDP — —
n+2 LDF POP LDP —
n+3 LDI LDF POP LDP
n+4 PUSHF LDI LDF POP
n+5 PUSH PUSHF LDI LDF
- TMS320C3x 1
- User’s Guide 1
- Read This First 3
- Notational Conventions 4
- Information About Cautions 5
- References 6
- References 7
- Read This First 7
- Array Signal 9
- Processing 9
- Adaptive Array Principles 9
- If You Need Assistance . . 10
- Trademarks 11
- Contents 12
- Contents 14
- Contents 14
- Figures 20
- Examples 27
- Examples 28
- Introduction 30
- 1.1 TMS320C3x Devices 31
- 1.1.2 TMS320C30 32
- 1.1.4 TMS320C32 33
- TMS320C3x Devices 34
- 1.2 Typical Applications 36
- Architectural Overview 37
- 2.1 Overview 38
- Overview 39
- Central Processing Unit (CPU) 42
- Operation 44
- Addressing 44
- 2.3 CPU Primary Register File 45
- Data Formats and 46
- Floating-Point Operation 46
- CPU Primary Register File 47
- 2.4 Other Registers 48
- 2.5 Memory Organization 49
- Memory Organization 50
- 2.5.2 Memory Addressing Modes 53
- 2.6 Internal Bus Operation 54
- 2.7 External Memory Interface 55
- External Memory Interface 56
- 2.8 Interrupts 57
- 2.9 Peripherals 58
- 2.9.1 Timers 59
- 2.9.2 Serial Ports 59
- Figure 2–10. DMA Controller 61
- CPU Registers 64
- Table 3–1. CPU Registers 65
- 3.1.3 Data-Page Pointer (DP) 67
- 3.1.7 Status (ST) Register 68
- CPU Multiport Register File 69
- (TMS320C30 and TMS320C31) 72
- 3.2 Other Registers 81
- Chapter 4 83
- 4.1 Memory 84
- Peripheral Bus Memory Map 85
- 4.1.1.2 TMS320C31 Memory Map 87
- Reset/Interrupt/ 87
- Trap Vector Map 87
- Data-Page Pointer (DP) 88
- 4.1.1.3 TMS320C32 Memory Map 89
- ’C31, and ’C32 91
- Interrupt-Trap Table 96
- Pointer (ITTP) 96
- Microprocessor Mode 97
- Microcomputer Mode 99
- Note: Traps 28–31 100
- 4.3 Instruction Cache 101
- Instruction Cache 102
- 4.3.3 Cache Control Bits 104
- Chapter 5 106
- 5.1 Integer Formats 107
- 5.2 Unsigned-Integer Formats 108
- 5.3 Floating-Point Formats 109
- Floating-Point Formats 110
- Example 5–1. Positive Number 115
- Example 5–2. Negative Number 116
- Floating-Point Format 117
- (the actual expo 119
- ±1,R0 ; Add the positive sign 128
- Floating-Point Multiplication 132
- 0–α =–α (α ≠ 0) 141
- Rounding (RND Instruction) 144
- Mantissa 150
- 5.11.2 Points to Consider 152
- Addressing Modes 154
- 6.1 Addressing Types 155
- 6.2 Register Addressing 156
- 6.3 Direct Addressing 157
- 6.4 Indirect Addressing 158
- Indirect Addressing 159
- 6.5 Immediate Addressing 171
- 6.6 PC-Relative Addressing 172
- PC-Relative Addressing 173
- (c) RPTB: repeat block 173
- 6.7 Circular Addressing 174
- Circular Addressing 176
- 6.8 Bit-Reversed Addressing 179
- Bit-Reversed Addressing 180
- Language Tools 181
- 6.10.1 System-Stack Pointer 182
- 6.10.2 Stacks 183
- 6.10.3 Queues 184
- Program Flow Control 185
- 7.1 Repeat Modes 186
- 7.1.2 Repeat-Mode Operation 187
- Example 7–2. RPTB Operation 188
- 7.1.4 RPTS Instruction 189
- Repeat Modes 190
- 7.1.7 Nested Block Repeats 192
- 7.2 Delayed Branches 193
- Delayed Branches 194
- 7.3 Calls, Traps, and Returns 195
- Calls, Traps, and Returns 196
- 7.4 Interlocked Operations 197
- Interlocked Operations 198
- I/O Flag Register (IOF) 203
- (see Example 7–14) 204
- 7.5 Reset Operation 205
- Reset Operation 206
- Peripherals 209
- ’C30 and ’C31 External-Memory 209
- Interface 209
- 7.6 Interrupts 210
- TMS320C31 Microprocessor Mode 211
- Microcomputer Boot Mode 212
- Interrupts 213
- 7.6.6 Interrupt Processing 217
- Note: CPU and DMA Interrupts 218
- 7.6.7 CPU Interrupt Latency 219
- Table 7–8. Interrupt Latency 220
- 7.7 DMA Interrupts 222
- DMA Interrupts 223
- 7.7.3 CPU/DMA Interaction 224
- ... ; GIE = 1 226
- LDI 02000h, ST ; GIE = 0 226
- ADD *AR0, R1 226
- 7.8 Traps 231
- 7.9 Power Management Modes 233
- Figure 7–11.IDLE2 Timing 234
- 7.9.2 LOPOWER 235
- Figure 7–13. LOPOWER Timing 236
- Figure 7–14. MAXSPEED Timing 236
- Pipeline Operation 237
- 8.1 Pipeline Structure 238
- Pipeline Structure 239
- 8.2 Pipeline Conflicts 240
- Example 8–1. Standard Branch 241
- Example 8–2. Delayed Branch 242
- LDI 7,AR2 ; 7 → AR2 243
- 8.2.3 Memory Conflicts 244
- 8.2.3.1 Program Wait 245
- ADDF3 *AR0,*AR1,R0 246
- MPY ; code in internal memory 247
- 8.2.3.3 Execute Only 248
- → R1 in parallel with 249
- LDF *AR3,R2 ; *AR3 → R2 249
- STF R2,*AR1 ; R2 → *AR1 250
- ADDF @SUM,R1 ; R1 + @SUM → R1 250
- 8.2.3.4 Hold Everything 251
- STF R0,@DMA1 252
- LDF @DMA2,R0 252
- LDF @DMA,R0 253
- Generation 255
- Pipeline Conflict 256
- Resolving Register Conflicts 257
- 8.5 Clocking Memory Accesses 260
- Clocking Memory Accesses 261
- Example 8–17. Dummy sr2 Read 263
- ; AR1 points to MSTRB space ( 264
- TMS320C30 and TMS320C31 267
- External-Memory Interface 267
- 9.1 Overview 268
- 9.2 Memory Interface Signals 269
- Memory Interface Signals 270
- 9.4 Programmable Wait States 276
- Programmable Wait States 277
- Figure 9–4. BNKCMP Example 278
- Programmable Bank Switching 279
- 9.6.1 Primary-Bus Cycles 281
- changes 284
- is sampled, it is 0 285
- The next time (X)RDY 286
- 9.6.3 Hold Cycles 303
- TMS320C32 Memory Features 305
- TMS320C32 Memory Overview 306
- 10.2.2 Program Memory Access 307
- Figure 10–2. Status Register 308
- External 16-Bit Data 309
- 10.3 Configuration 310
- Configuration 311
- 10.4 Programmable Wait States 318
- Figure 10–8. BNKCMP Example 320
- 32-Bit-Wide Memory Interface 323
- 16-Bit-Wide Memory Interface 329
- 8-Bit-Wide Memory Interface 335
- 10.10 Bus Timing 342
- Bus Timing 343
- 10.10.2 IOSTRB Bus Cycles 345
- 10.10.3 Inactive Bus States 354
- Using the TMS320C31 and 356
- TMS320C32 Boot Loaders 356
- 11.1 TMS320C31 Boot Loader 357
- TMS320C31 Boot Loader 358
- 11.1.4.2 Serial-Port Loading 366
- 11.2 TMS320C32 Boot Loader 369
- TMS320C32 Boot Loader 370
- SSSSSS6x 377
- 12.1 Timers 381
- 12.1.1 Timer Pins 382
- Timer Operation Modes 384
- 12.1.5 Timer Pulse Generation 386
- Figure 12–4. Timer Timing 387
- = 0 (pulse mode) 388
- 12.1.6 Timer Operation Modes 389
- 12.1.8 Timer Interrupts 392
- 12.2 Serial Ports 394
- Serial Ports 395
- It is also set to 0 at reset 406
- 12.2.7 Data-Transmit Register 407
- 12.2.8 Data-Receive Register 407
- 12.2.10 Serial-Port Timing 410
- 12.2.10.2 Handshake Mode 412
- 12.3 DMA Controller 427
- DMA Controller 428
- 12.3.2 DMA Basic Operation 429
- 12.3.3 DMA Registers 430
- Interrupt-Enable Register 439
- Clocking Memory Access 442
- 12.3.7 DMA and Interrupts 443
- Chapter 13 459
- 13.1 Instruction Set 460
- 13.1.2 2-Operand Instructions 461
- 13.1.3 3-Operand Instructions 462
- Instruction Set 464
- 13.1.8 Illegal Instructions 467
- 13.2 Instruction Set Summary 468
- General Addressing Modes 478
- field. Refer to 479
- B 0 0 0 485
- Condition Codes and Flags 486
- Figure 13–6. Status Register 487
- (a) Unconditional compares 488
- (b) Unsigned compares 488
- (c) Signed compares 488
- (d) Compare to zero 489
- 13.6 Individual Instructions 490
- Individual Instructions 492
- Note the alternate notation R 494
- Example Instruction 496
- Example Instruction 497
- ABSF 500
- Absolute Value of Integer 502
- Example 1 ABSI R0,R0 503
- Example 2 ABSI *AR1,R3 503
- ABSI 504
- Add Integer With Carry 506
- 31 2423 16 8 7 015 507
- 00100 0 T 507
- Data Loads and Stores 508
- Add Floating-Point Values 509
- Example ADDF *AR4++(IR1),R5 510
- ADDF3 513
- Add Integer 515
- Add Integer, 3-Operand 516
- ADDI3 518
- ADDl3 519
- Bitwise-Logical AND 520
- 31 24 23 16 8 7 015 521
- AND3 523
- Example ANDN @980Ch,R2 526
- Arithmetic Shift 529
- Arithmetic Shift 530
- Arithmetic Shift, 3-Operand 531
- Arithmetic Shift, 3-Operand 532
- ASH3 534
- 01101 00 537
- B0 Register or displacement00 537
- Example BZ R0 538
- B0 Register or displacement01 539
- Call Subroutine 543
- CALLcond 544
- Compare Floating-Point Value 546
- Example CMPF *+AR4,R6 547
- 0010 0110 548
- Compare Integer 550
- Compare Integer, 3-Operand 551
- Register or displacementAR 553
- Example FIX R1,R2 558
- FIX 559
- Example FLOAT *++AR2(2),R5 562
- FLOAT 563
- Interrupt Acknowledge 565
- Example IACK *AR5 566
- Idle Until Interrupt 567
- Low-Power Idle 568
- Low-Power Idle 569
- Load Floating-Point Exponent 570
- Example LDE R0,R5 571
- Load Floating-Point Value 572
- Example LDFZ R3,R5 574
- 000 00 1 575
- Example LDFI *+AR2,R7 576
- LDF 577
- LDF 579
- Load Integer 581
- Example LDI *–AR1(IR0),R5 582
- Load Integer Conditionally 583
- Example LDIZ *ARO++,R6 584
- Load Integer, Interlocked 585
- Example LDII @985Fh,R3 586
- LDI 587
- LDI 589
- Load Floating-Point Mantissa 591
- Load Data-Page Pointer 592
- Divide Clock by 16 593
- Logical Shift 594
- Logical Shift 595
- Logical Shift, 3-Operand 596
- Logical Shift, 3-Operand 597
- LSH3 599
- MAXSPEED 603
- Multiply Floating-Point Value 604
- MPYF3 607
- MPYF3 611
- MPYF3 613
- Multiply Integer 617
- Example MPYI R1,R5 618
- Multiply Integer, 3-Operand 619
- MPYI3 621
- MPYl3 624
- MPYI3 625
- MPYI3 627
- Negative Integer With Borrow 631
- Negate Floating-Point Value 632
- Example NEGF *++AR3(2),R1 633
- NEGF 634
- Negate Integer 636
- NEGI 637
- No Operation 639
- Normalize 640
- Example NORM R1,R2 641
- Bitwise-Logical Complement 642
- Example NOT @982Ch,R4 643
- NOT 644
- Bitwise-Logical OR 646
- Example OR *++AR1(IR1),R2 647
- Bitwise-Logical OR, 3-Operand 648
- OR3 650
- Pop Integer 652
- Pop Floating-Point Value 653
- PUSH Integer 654
- PUSH Floating-Point Value 655
- RETIcond 656
- RETScond 658
- Round Floating-Point Value 660
- Round Floating-Point Value 661
- Rotate Left 662
- Rotate Left Through Carry 663
- Example 2 ROLC R3 664
- Rotate Right 665
- Rotate Right Through Carry 666
- Repeat Block 667
- Repeat Block 668
- Repeat Single Instruction 669
- Repeat Single Instruction 670
- Store Floating-Point Value 672
- STF 675
- Store Integer 677
- Store Integer, Interlocked 678
- STI 679
- Subtract Integer With Borrow 681
- 00 0 10 1 684
- Example 1 SUBC @98C5h,R1 685
- Subtract Floating-Point Value 686
- Example SUBF *AR0––(IR0),R5 687
- SUBF3 690
- Subtract Integer 692
- Subtract Integer, 3-Operand 693
- SUBI3 695
- Subtract Reverse Integer 699
- Software Interrupt 700
- TRAPcond 701
- Test Bit Fields 703
- Example TSTB *–AR4(1),R5 704
- Test Bit Fields, 3-Operand 705
- Bitwise-Exclusive OR 707
- XOR3 710
- Instruction Opcodes 712
- Instruction Opcodes 714
- Instruction Opcodes 714
- Appendix A 718
- Appendix B 718
- Appendix C 724
- Glossary 734
- Block-size register 735
- Central processing unit 735
- See also LD0–LD31 735
- First-in, first-out buffer 736
- Interrupt acknowledge signal 737
- Interrupt service routine 737
- Least significant bit 737
- CPU cycle 738
- MP/MC pin 738
- Most significant bit 738
- Nonmaskable interrupt 738
- Program counte 739
- See read/write pin 739
- Glossary 740
- Glossary 740
- See also A0–A23 741
- See also 741
- 3-operand instruction 13-58 742
- 3-operand instruction 13-49 742
- TMS320C32 2-16 749
- (LDF) 13-114 750
- TMS320C30 4-9 751
- TMS320C31 4-11 751
- TMS320C32 4-12 751
- (SUBRI) 13-241 756
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