Texas-instruments TMS320C3x Manual de usuario descargar pdf (Pagina 314)

100

101

Configuration

10-11

TMS320C32 Enhanced External Memory Interface

Table 10–1. STRB0, STRB1, and IOSTRB Control Register Bits (Continued)

Abbreviation DescriptionName

Reset

Value

Physical

memory width

(STRB0 and STRB1

control registers only)

Indicates the size of the physical memory connected to the

device. The “reset” value depends on the status of the

PRGW pin. If the PRGW pin is logic low, the memory width

is configured to 32 bits (= 11

). If the PRGW pin is logic high,

the physical memory width is configured to 16 bits (= 01

This field can have the following values:

Bit 17 Bit 16 Data Type Size

0 0 8 bit

0 1 16 bit (reset value if PRGW = 1)

1 0 Reserved

1 1 32 bit (reset value if PRGW = 0)

Setting the physical memory width field of the STRB0

STRB1

control registers changes the functionality of the

STRB0

or STRB1 signals.

When the physical memory width field is configured to 32

bits, the corresponding STRBx_B0

–STRBx_B3 signals

are configured as byte-enable pins (see Figure 10–10

on page 10-20).

When the physical memory width field is configured to

16 bits, the corresponding STRBx_B3/A–1 signal is

configured as an address pin while the STRBx_B0

and

STRBx_B1

signals are configured as byte-enable pins

(see Figure 10–14 on page 10-26).

When the physical memory width field is configured to

8 bits, the STRBx_B3/A–3 and STRBx_B2/A–2 signals

are configured as byte-enable pins (see Figure 10–18

on page 10-32).

Once an STRBx_Bx

signal is configured as an address pin,

it is active for any external memory access (STRB0

, STRB1,

IOSTRB, or external fetch).

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