Texas-instruments TMS320C3x Manual de usuario descargar pdf (Pagina 640)

100

101

NORM

Normalize

13-182

Syntax NORM

src, dst

Operation norm (

src

) →

dst

Operands

src

general addressing modes (G):

0 0 register (R

, 0 ≤

≤ 7)

0 1 direct

1 0 indirect (disp = 0–255, IR0, IR1)

1 1 immediate

Opcode

31 24 23 16 8 7 015

00 0 01 1

0 01

dst src

Description The

src

operand is assumed to be an unnormalized floating-point number; that

is, the implied bit is set equal to the sign bit. The

dst

is set equal to the normal-

ized

src

operand with the implied bit removed. The

dst

operand exponent is

set to the

src

operand exponent minus the size of the left shift necessary to

normalize the

src

. The

dst

operand is assumed to be a normalized floating-

point number.

src (exp

) = –128 and

src (man

) = 0, then

dst

= 0, Z = 1, and UF = 0.

src

(

exp

) = –128 and

src

(

man

) ≠ 0, then

dst

= 0, Z = 0, and UF = 1.

For all other cases of the

src,

if a floating-point underflow occurs, then

dst (man

) is forced to 0 and

dst (exp

) = –128.

src (man

) = 0, then

dst (man

) = 0 and

dst (exp

) = –128.

Refer to Section 5.7,

Normalization Using the NORM Instruction

, on page 5-37

for more information.

Cycles 1

Status Bits These condition flags are modified only if the destination register is R7–R0.

LUF 1 if a floating-point underflow occurs; unchanged otherwise

LV Unaffected

UF 1 if a floating-point underflow occurs; 0 otherwise

N 1 if a negative result is generated; 0 otherwise

Z 1 if a 0 result is generated; 0 otherwise

V 0

C Unaffected

OVM Operation is not affected by OVM bit value.

Mode Bit

1 2 ... 635 636 637 638 639 640 641 642 643 644 645 ... 756 757

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Texas-instruments TMS320C3x Manual de usuario Pagina 640

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